Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 3 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 4 | #include <commonlib/helpers.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 5 | #include <console/console.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 6 | #include <device/pci_ops.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 7 | #include <arch/acpi.h> |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 8 | #include <arch/acpi_ivrs.h> |
Michał Żygowski | 208318c | 2020-03-20 15:54:27 +0100 | [diff] [blame] | 9 | #include <arch/ioapic.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 10 | #include <stdint.h> |
| 11 | #include <device/device.h> |
| 12 | #include <device/pci.h> |
| 13 | #include <device/pci_ids.h> |
| 14 | #include <device/hypertransport.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 15 | #include <string.h> |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 16 | #include <stdlib.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 17 | #include <lib.h> |
| 18 | #include <cpu/cpu.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 19 | #include <Porting.h> |
| 20 | #include <AGESA.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 21 | #include <Topology.h> |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 22 | #include <cpu/x86/lapic.h> |
| 23 | #include <cpu/amd/msr.h> |
| 24 | #include <cpu/amd/mtrr.h> |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 25 | #include <arch/acpigen.h> |
Kyösti Mälkki | bbd2377 | 2019-01-10 05:41:23 +0200 | [diff] [blame] | 26 | #include <northbridge/amd/pi/nb_common.h> |
Kyösti Mälkki | ed8d277 | 2017-07-15 17:12:44 +0300 | [diff] [blame] | 27 | #include <northbridge/amd/agesa/agesa_helper.h> |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 28 | #include <southbridge/amd/pi/hudson/pci_devs.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 29 | |
Kyösti Mälkki | 113f670 | 2018-05-20 20:12:32 +0300 | [diff] [blame] | 30 | #define MAX_NODE_NUMS MAX_NODES |
Michał Żygowski | 6ca5b47 | 2019-09-10 15:10:22 +0200 | [diff] [blame] | 31 | #define PCIE_CAP_AER BIT(5) |
| 32 | #define PCIE_CAP_ACS BIT(6) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 33 | |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 34 | typedef struct dram_base_mask { |
| 35 | u32 base; //[47:27] at [28:8] |
| 36 | u32 mask; //[47:27] at [28:8] and enable at bit 0 |
| 37 | } dram_base_mask_t; |
| 38 | |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 39 | static unsigned int node_nums; |
| 40 | static unsigned int sblink; |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 41 | static struct device *__f0_dev[MAX_NODE_NUMS]; |
| 42 | static struct device *__f1_dev[MAX_NODE_NUMS]; |
| 43 | static struct device *__f2_dev[MAX_NODE_NUMS]; |
| 44 | static struct device *__f4_dev[MAX_NODE_NUMS]; |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 45 | static unsigned int fx_devs = 0; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 46 | |
| 47 | static dram_base_mask_t get_dram_base_mask(u32 nodeid) |
| 48 | { |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 49 | struct device *dev; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 50 | dram_base_mask_t d; |
| 51 | dev = __f1_dev[0]; |
| 52 | u32 temp; |
| 53 | temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] |
| 54 | d.mask = ((temp & 0xfff80000)>>(8+3)); // mask out DramMask [26:24] too |
| 55 | temp = pci_read_config32(dev, 0x144 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] |
| 56 | d.mask |= temp<<21; |
| 57 | temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] |
| 58 | d.mask |= (temp & 1); // enable bit |
| 59 | d.base = ((temp & 0xfff80000)>>(8+3)); // mask out DramBase [26:24) too |
| 60 | temp = pci_read_config32(dev, 0x140 + (nodeid <<3)) & 0xff; //[47:40] at [7:0] |
| 61 | d.base |= temp<<21; |
| 62 | return d; |
| 63 | } |
| 64 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 65 | static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 66 | u32 io_min, u32 io_max) |
| 67 | { |
| 68 | u32 i; |
| 69 | u32 tempreg; |
| 70 | /* io range allocation */ |
| 71 | tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | ((io_max&0xf0)<<(12-4)); //limit |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 72 | for (i = 0; i < node_nums; i++) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 73 | pci_write_config32(__f1_dev[i], reg+4, tempreg); |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 74 | tempreg = 3 /*| (3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ? |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 75 | for (i = 0; i < node_nums; i++) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 76 | pci_write_config32(__f1_dev[i], reg, tempreg); |
| 77 | } |
| 78 | |
| 79 | static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes) |
| 80 | { |
| 81 | u32 i; |
| 82 | u32 tempreg; |
| 83 | /* io range allocation */ |
| 84 | tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 85 | for (i = 0; i < nodes; i++) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 86 | pci_write_config32(__f1_dev[i], reg+4, tempreg); |
| 87 | tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 88 | for (i = 0; i < node_nums; i++) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 89 | pci_write_config32(__f1_dev[i], reg, tempreg); |
| 90 | } |
| 91 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 92 | static struct device *get_node_pci(u32 nodeid, u32 fn) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 93 | { |
Kyösti Mälkki | bbd2377 | 2019-01-10 05:41:23 +0200 | [diff] [blame] | 94 | return pcidev_on_root(DEV_CDB + nodeid, fn); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 95 | } |
| 96 | |
| 97 | static void get_fx_devs(void) |
| 98 | { |
| 99 | int i; |
| 100 | for (i = 0; i < MAX_NODE_NUMS; i++) { |
| 101 | __f0_dev[i] = get_node_pci(i, 0); |
| 102 | __f1_dev[i] = get_node_pci(i, 1); |
| 103 | __f2_dev[i] = get_node_pci(i, 2); |
| 104 | __f4_dev[i] = get_node_pci(i, 4); |
| 105 | if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) |
| 106 | fx_devs = i+1; |
| 107 | } |
| 108 | if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { |
| 109 | die("Cannot find 0:0x18.[0|1]\n"); |
| 110 | } |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 111 | printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 112 | } |
| 113 | |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 114 | static u32 f1_read_config32(unsigned int reg) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 115 | { |
| 116 | if (fx_devs == 0) |
| 117 | get_fx_devs(); |
| 118 | return pci_read_config32(__f1_dev[0], reg); |
| 119 | } |
| 120 | |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 121 | static void f1_write_config32(unsigned int reg, u32 value) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 122 | { |
| 123 | int i; |
| 124 | if (fx_devs == 0) |
| 125 | get_fx_devs(); |
Elyes HAOUAS | 5a7e72f | 2016-08-23 21:36:02 +0200 | [diff] [blame] | 126 | for (i = 0; i < fx_devs; i++) { |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 127 | struct device *dev; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 128 | dev = __f1_dev[i]; |
| 129 | if (dev && dev->enabled) { |
| 130 | pci_write_config32(dev, reg, value); |
| 131 | } |
| 132 | } |
| 133 | } |
| 134 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 135 | static u32 amdfam16_nodeid(struct device *dev) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 136 | { |
Kyösti Mälkki | bbd2377 | 2019-01-10 05:41:23 +0200 | [diff] [blame] | 137 | return (dev->path.pci.devfn >> 3) - DEV_CDB; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 138 | } |
| 139 | |
| 140 | static void set_vga_enable_reg(u32 nodeid, u32 linkn) |
| 141 | { |
| 142 | u32 val; |
| 143 | |
| 144 | val = 1 | (nodeid<<4) | (linkn<<12); |
| 145 | /* it will routing |
| 146 | * (1)mmio 0xa0000:0xbffff |
| 147 | * (2)io 0x3b0:0x3bb, 0x3c0:0x3df |
| 148 | */ |
| 149 | f1_write_config32(0xf4, val); |
| 150 | |
| 151 | } |
| 152 | |
| 153 | /** |
| 154 | * @return |
Elyes HAOUAS | 99b075a | 2019-12-30 14:29:31 +0100 | [diff] [blame] | 155 | * @retval 2 resource does not exist, usable |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 156 | * @retval 0 resource exists, not usable |
| 157 | * @retval 1 resource exist, resource has been allocated before |
| 158 | */ |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 159 | static int reg_useable(unsigned int reg, struct device *goal_dev, |
| 160 | unsigned int goal_nodeid, unsigned int goal_link) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 161 | { |
| 162 | struct resource *res; |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 163 | unsigned int nodeid, link = 0; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 164 | int result; |
| 165 | res = 0; |
| 166 | for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 167 | struct device *dev; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 168 | dev = __f0_dev[nodeid]; |
| 169 | if (!dev) |
| 170 | continue; |
| 171 | for (link = 0; !res && (link < 8); link++) { |
| 172 | res = probe_resource(dev, IOINDEX(0x1000 + reg, link)); |
| 173 | } |
| 174 | } |
| 175 | result = 2; |
| 176 | if (res) { |
| 177 | result = 0; |
| 178 | if ((goal_link == (link - 1)) && |
| 179 | (goal_nodeid == (nodeid - 1)) && |
| 180 | (res->flags <= 1)) { |
| 181 | result = 1; |
| 182 | } |
| 183 | } |
| 184 | return result; |
| 185 | } |
| 186 | |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 187 | static struct resource *amdfam16_find_iopair(struct device *dev, |
| 188 | unsigned int nodeid, unsigned int link) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 189 | { |
| 190 | struct resource *resource; |
| 191 | u32 free_reg, reg; |
| 192 | resource = 0; |
| 193 | free_reg = 0; |
| 194 | for (reg = 0xc0; reg <= 0xd8; reg += 0x8) { |
| 195 | int result; |
| 196 | result = reg_useable(reg, dev, nodeid, link); |
| 197 | if (result == 1) { |
| 198 | /* I have been allocated this one */ |
| 199 | break; |
| 200 | } |
| 201 | else if (result > 1) { |
| 202 | /* I have a free register pair */ |
| 203 | free_reg = reg; |
| 204 | } |
| 205 | } |
| 206 | if (reg > 0xd8) { |
| 207 | reg = free_reg; // if no free, the free_reg still be 0 |
| 208 | } |
| 209 | |
| 210 | resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); |
| 211 | |
| 212 | return resource; |
| 213 | } |
| 214 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 215 | static struct resource *amdfam16_find_mempair(struct device *dev, u32 nodeid, u32 link) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 216 | { |
| 217 | struct resource *resource; |
| 218 | u32 free_reg, reg; |
| 219 | resource = 0; |
| 220 | free_reg = 0; |
| 221 | for (reg = 0x80; reg <= 0xb8; reg += 0x8) { |
| 222 | int result; |
| 223 | result = reg_useable(reg, dev, nodeid, link); |
| 224 | if (result == 1) { |
| 225 | /* I have been allocated this one */ |
| 226 | break; |
| 227 | } |
| 228 | else if (result > 1) { |
| 229 | /* I have a free register pair */ |
| 230 | free_reg = reg; |
| 231 | } |
| 232 | } |
| 233 | if (reg > 0xb8) { |
| 234 | reg = free_reg; |
| 235 | } |
| 236 | |
| 237 | resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); |
| 238 | return resource; |
| 239 | } |
| 240 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 241 | static void amdfam16_link_read_bases(struct device *dev, u32 nodeid, u32 link) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 242 | { |
| 243 | struct resource *resource; |
| 244 | |
| 245 | /* Initialize the io space constraints on the current bus */ |
| 246 | resource = amdfam16_find_iopair(dev, nodeid, link); |
| 247 | if (resource) { |
| 248 | u32 align; |
| 249 | align = log2(HT_IO_HOST_ALIGN); |
| 250 | resource->base = 0; |
| 251 | resource->size = 0; |
| 252 | resource->align = align; |
| 253 | resource->gran = align; |
| 254 | resource->limit = 0xffffUL; |
| 255 | resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE; |
| 256 | } |
| 257 | |
| 258 | /* Initialize the prefetchable memory constraints on the current bus */ |
| 259 | resource = amdfam16_find_mempair(dev, nodeid, link); |
| 260 | if (resource) { |
| 261 | resource->base = 0; |
| 262 | resource->size = 0; |
| 263 | resource->align = log2(HT_MEM_HOST_ALIGN); |
| 264 | resource->gran = log2(HT_MEM_HOST_ALIGN); |
| 265 | resource->limit = 0xffffffffffULL; |
| 266 | resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; |
| 267 | resource->flags |= IORESOURCE_BRIDGE; |
| 268 | } |
| 269 | |
| 270 | /* Initialize the memory constraints on the current bus */ |
| 271 | resource = amdfam16_find_mempair(dev, nodeid, link); |
| 272 | if (resource) { |
| 273 | resource->base = 0; |
| 274 | resource->size = 0; |
| 275 | resource->align = log2(HT_MEM_HOST_ALIGN); |
| 276 | resource->gran = log2(HT_MEM_HOST_ALIGN); |
| 277 | resource->limit = 0xffffffffffULL; |
| 278 | resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; |
| 279 | } |
| 280 | |
| 281 | } |
| 282 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 283 | static void read_resources(struct device *dev) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 284 | { |
| 285 | u32 nodeid; |
| 286 | struct bus *link; |
Michał Żygowski | 208318c | 2020-03-20 15:54:27 +0100 | [diff] [blame] | 287 | struct resource *res; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 288 | |
| 289 | nodeid = amdfam16_nodeid(dev); |
| 290 | for (link = dev->link_list; link; link = link->next) { |
| 291 | if (link->children) { |
| 292 | amdfam16_link_read_bases(dev, nodeid, link->link_num); |
| 293 | } |
| 294 | } |
Kyösti Mälkki | 5d49038 | 2015-05-27 07:58:22 +0300 | [diff] [blame] | 295 | |
| 296 | /* |
| 297 | * This MMCONF resource must be reserved in the PCI domain. |
| 298 | * It is not honored by the coreboot resource allocator if it is in |
| 299 | * the CPU_CLUSTER. |
| 300 | */ |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 301 | mmconf_resource(dev, MMIO_CONF_BASE); |
Michał Żygowski | 208318c | 2020-03-20 15:54:27 +0100 | [diff] [blame] | 302 | |
| 303 | /* NB IOAPIC2 resource */ |
| 304 | res = new_resource(dev, IO_APIC2_ADDR); /* IOAPIC2 */ |
| 305 | res->base = IO_APIC2_ADDR; |
| 306 | res->size = 0x00001000; |
| 307 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 308 | } |
| 309 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 310 | static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 311 | { |
| 312 | resource_t rbase, rend; |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 313 | unsigned int reg, link_num; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 314 | char buf[50]; |
| 315 | |
| 316 | /* Make certain the resource has actually been set */ |
| 317 | if (!(resource->flags & IORESOURCE_ASSIGNED)) { |
| 318 | return; |
| 319 | } |
| 320 | |
| 321 | /* If I have already stored this resource don't worry about it */ |
| 322 | if (resource->flags & IORESOURCE_STORED) { |
| 323 | return; |
| 324 | } |
| 325 | |
| 326 | /* Only handle PCI memory and IO resources */ |
| 327 | if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) |
| 328 | return; |
| 329 | |
| 330 | /* Ensure I am actually looking at a resource of function 1 */ |
| 331 | if ((resource->index & 0xffff) < 0x1000) { |
| 332 | return; |
| 333 | } |
| 334 | /* Get the base address */ |
| 335 | rbase = resource->base; |
| 336 | |
| 337 | /* Get the limit (rounded up) */ |
| 338 | rend = resource_end(resource); |
| 339 | |
| 340 | /* Get the register and link */ |
| 341 | reg = resource->index & 0xfff; // 4k |
| 342 | link_num = IOINDEX_LINK(resource->index); |
| 343 | |
| 344 | if (resource->flags & IORESOURCE_IO) { |
| 345 | set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); |
| 346 | } |
| 347 | else if (resource->flags & IORESOURCE_MEM) { |
Elyes HAOUAS | 7db506c | 2016-10-02 11:56:39 +0200 | [diff] [blame] | 348 | set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums); // [39:8] |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 349 | } |
| 350 | resource->flags |= IORESOURCE_STORED; |
Elyes HAOUAS | 0d4b11a | 2016-10-03 21:57:21 +0200 | [diff] [blame] | 351 | snprintf(buf, sizeof(buf), " <node %x link %x>", |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 352 | nodeid, link_num); |
| 353 | report_resource_stored(dev, resource, buf); |
| 354 | } |
| 355 | |
| 356 | /** |
| 357 | * I tried to reuse the resource allocation code in set_resource() |
| 358 | * but it is too difficult to deal with the resource allocation magic. |
| 359 | */ |
| 360 | |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 361 | static void create_vga_resource(struct device *dev, unsigned int nodeid) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 362 | { |
| 363 | struct bus *link; |
| 364 | |
| 365 | /* find out which link the VGA card is connected, |
| 366 | * we only deal with the 'first' vga card */ |
| 367 | for (link = dev->link_list; link; link = link->next) { |
| 368 | if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 369 | #if CONFIG(MULTIPLE_VGA_ADAPTERS) |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 370 | extern struct device *vga_pri; // the primary vga device, defined in device.c |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 371 | printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, |
| 372 | link->secondary,link->subordinate); |
| 373 | /* We need to make sure the vga_pri is under the link */ |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 374 | if ((vga_pri->bus->secondary >= link->secondary) && |
| 375 | (vga_pri->bus->secondary <= link->subordinate)) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 376 | #endif |
| 377 | break; |
| 378 | } |
| 379 | } |
| 380 | |
| 381 | /* no VGA card installed */ |
| 382 | if (link == NULL) |
| 383 | return; |
| 384 | |
| 385 | printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, sblink); |
| 386 | set_vga_enable_reg(nodeid, sblink); |
| 387 | } |
| 388 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 389 | static void set_resources(struct device *dev) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 390 | { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 391 | unsigned int nodeid; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 392 | struct bus *bus; |
| 393 | struct resource *res; |
| 394 | |
| 395 | /* Find the nodeid */ |
| 396 | nodeid = amdfam16_nodeid(dev); |
| 397 | |
| 398 | create_vga_resource(dev, nodeid); //TODO: do we need this? |
| 399 | |
| 400 | /* Set each resource we have found */ |
| 401 | for (res = dev->resource_list; res; res = res->next) { |
| 402 | set_resource(dev, res, nodeid); |
| 403 | } |
| 404 | |
| 405 | for (bus = dev->link_list; bus; bus = bus->next) { |
| 406 | if (bus->children) { |
| 407 | assign_resources(bus); |
| 408 | } |
| 409 | } |
| 410 | } |
| 411 | |
| 412 | static void northbridge_init(struct device *dev) |
| 413 | { |
Michał Żygowski | 208318c | 2020-03-20 15:54:27 +0100 | [diff] [blame] | 414 | setup_ioapic((u8 *)IO_APIC2_ADDR, CONFIG_MAX_CPUS+1); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 415 | } |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 416 | |
Vladimir Serbinenko | 807127f | 2014-11-09 13:36:18 +0100 | [diff] [blame] | 417 | static unsigned long acpi_fill_hest(acpi_hest_t *hest) |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 418 | { |
| 419 | void *addr, *current; |
| 420 | |
| 421 | /* Skip the HEST header. */ |
| 422 | current = (void *)(hest + 1); |
| 423 | |
| 424 | addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); |
| 425 | if (addr != NULL) |
| 426 | current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); |
| 427 | |
| 428 | addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); |
| 429 | if (addr != NULL) |
| 430 | current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); |
| 431 | |
| 432 | return (unsigned long)current; |
| 433 | } |
| 434 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 435 | unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current) |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 436 | { |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 437 | /* 8-byte IVHD structures must be aligned to the 8-byte boundary. */ |
| 438 | current = ALIGN_UP(current, 8); |
| 439 | ivrs_ivhd_special_t *ivhd_ioapic = (ivrs_ivhd_special_t *)current; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 440 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 441 | ivhd_ioapic->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; |
| 442 | ivhd_ioapic->reserved = 0x0000; |
| 443 | ivhd_ioapic->dte_setting = IVHD_DTE_LINT_1_PASS | IVHD_DTE_LINT_0_PASS | |
| 444 | IVHD_DTE_SYS_MGT_NO_TRANS | IVHD_DTE_NMI_PASS | |
| 445 | IVHD_DTE_EXT_INT_PASS | IVHD_DTE_INIT_PASS; |
| 446 | ivhd_ioapic->handle = CONFIG_MAX_CPUS; /* FCH IOAPIC ID */ |
| 447 | ivhd_ioapic->source_dev_id = PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC); |
| 448 | ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC; |
| 449 | current += sizeof(ivrs_ivhd_special_t); |
| 450 | |
| 451 | ivhd_ioapic = (ivrs_ivhd_special_t *)current; |
| 452 | |
| 453 | ivhd_ioapic->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; |
| 454 | ivhd_ioapic->reserved = 0x0000; |
| 455 | ivhd_ioapic->dte_setting = 0x00; |
| 456 | ivhd_ioapic->handle = CONFIG_MAX_CPUS + 1; /* GNB IOAPIC ID */ |
| 457 | ivhd_ioapic->source_dev_id = PCI_DEVFN(0, 1); |
| 458 | ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC; |
| 459 | current += sizeof(ivrs_ivhd_special_t); |
| 460 | |
| 461 | return current; |
| 462 | } |
| 463 | |
| 464 | static unsigned long ivhd_describe_hpet(unsigned long current) |
| 465 | { |
| 466 | /* 8-byte IVHD structures must be aligned to the 8-byte boundary. */ |
| 467 | current = ALIGN_UP(current, 8); |
| 468 | ivrs_ivhd_special_t *ivhd_hpet = (ivrs_ivhd_special_t *)current; |
| 469 | |
| 470 | ivhd_hpet->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; |
| 471 | ivhd_hpet->reserved = 0x0000; |
| 472 | ivhd_hpet->dte_setting = 0x00; |
| 473 | ivhd_hpet->handle = 0x00; |
| 474 | ivhd_hpet->source_dev_id = PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC); |
| 475 | ivhd_hpet->variety = IVHD_SPECIAL_DEV_HPET; |
| 476 | current += sizeof(ivrs_ivhd_special_t); |
| 477 | |
| 478 | return current; |
| 479 | } |
| 480 | |
| 481 | static unsigned long ivhd_dev_range(unsigned long current, uint16_t start_devid, |
| 482 | uint16_t end_devid, uint8_t setting) |
| 483 | { |
| 484 | /* 4-byte IVHD structures must be aligned to the 4-byte boundary. */ |
| 485 | current = ALIGN_UP(current, 4); |
| 486 | ivrs_ivhd_generic_t *ivhd_range = (ivrs_ivhd_generic_t *)current; |
| 487 | |
| 488 | /* Create the start range IVHD entry */ |
| 489 | ivhd_range->type = IVHD_DEV_4_BYTE_START_RANGE; |
| 490 | ivhd_range->dev_id = start_devid; |
| 491 | ivhd_range->dte_setting = setting; |
| 492 | current += sizeof(ivrs_ivhd_generic_t); |
| 493 | |
| 494 | /* Create the end range IVHD entry */ |
| 495 | ivhd_range = (ivrs_ivhd_generic_t *)current; |
| 496 | ivhd_range->type = IVHD_DEV_4_BYTE_END_RANGE; |
| 497 | ivhd_range->dev_id = end_devid; |
| 498 | ivhd_range->dte_setting = setting; |
| 499 | current += sizeof(ivrs_ivhd_generic_t); |
| 500 | |
| 501 | return current; |
| 502 | } |
| 503 | |
| 504 | static unsigned long add_ivhd_dev_entry(struct device *parent, struct device *dev, |
| 505 | unsigned long *current, uint8_t type, uint8_t data) |
| 506 | { |
| 507 | if (type == IVHD_DEV_4_BYTE_SELECT) { |
| 508 | /* 4-byte IVHD structures must be aligned to the 4-byte boundary. */ |
| 509 | *current = ALIGN_UP(*current, 4); |
| 510 | ivrs_ivhd_generic_t *ivhd_entry = (ivrs_ivhd_generic_t *)*current; |
| 511 | |
| 512 | ivhd_entry->type = type; |
| 513 | ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8); |
| 514 | ivhd_entry->dte_setting = data; |
| 515 | *current += sizeof(ivrs_ivhd_generic_t); |
| 516 | } else if (type == IVHD_DEV_8_BYTE_ALIAS_SELECT) { |
| 517 | /* 8-byte IVHD structures must be aligned to the 8-byte boundary. */ |
| 518 | *current = ALIGN_UP(*current, 8); |
| 519 | ivrs_ivhd_alias_t *ivhd_entry = (ivrs_ivhd_alias_t *)*current; |
| 520 | |
| 521 | ivhd_entry->type = type; |
| 522 | ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8); |
| 523 | ivhd_entry->dte_setting = data; |
| 524 | ivhd_entry->reserved1 = 0; |
| 525 | ivhd_entry->reserved2 = 0; |
| 526 | ivhd_entry->source_dev_id = parent->path.pci.devfn | |
| 527 | (parent->bus->secondary << 8); |
| 528 | *current += sizeof(ivrs_ivhd_alias_t); |
| 529 | } |
| 530 | |
| 531 | return *current; |
| 532 | } |
| 533 | |
| 534 | static void ivrs_add_device_or_bridge(struct device *parent, struct device *dev, |
| 535 | unsigned long *current, uint16_t *ivhd_length) |
| 536 | { |
| 537 | unsigned int header_type, is_pcie; |
| 538 | unsigned long current_backup; |
| 539 | |
| 540 | header_type = dev->hdr_type & 0x7f; |
| 541 | is_pcie = pci_find_capability(dev, PCI_CAP_ID_PCIE); |
| 542 | |
| 543 | if (((header_type == PCI_HEADER_TYPE_NORMAL) || |
| 544 | (header_type == PCI_HEADER_TYPE_BRIDGE)) && is_pcie) { |
| 545 | /* Device or Bridge is PCIe */ |
| 546 | current_backup = *current; |
| 547 | add_ivhd_dev_entry(parent, dev, current, IVHD_DEV_4_BYTE_SELECT, 0x0); |
| 548 | *ivhd_length += (*current - current_backup); |
| 549 | } else if ((header_type == PCI_HEADER_TYPE_NORMAL) && !is_pcie) { |
| 550 | /* Device is legacy PCI or PCI-X */ |
| 551 | current_backup = *current; |
| 552 | add_ivhd_dev_entry(parent, dev, current, IVHD_DEV_8_BYTE_ALIAS_SELECT, 0x0); |
| 553 | *ivhd_length += (*current - current_backup); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 554 | } |
| 555 | } |
| 556 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 557 | static void add_ivhd_device_entries(struct device *parent, struct device *dev, |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 558 | unsigned int depth, int linknum, int8_t *root_level, |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 559 | unsigned long *current, uint16_t *ivhd_length) |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 560 | { |
| 561 | struct device *sibling; |
| 562 | struct bus *link; |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 563 | |
| 564 | if (!root_level) { |
| 565 | root_level = malloc(sizeof(int8_t)); |
| 566 | *root_level = -1; |
| 567 | } |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 568 | |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 569 | if (dev->path.type == DEVICE_PATH_PCI) { |
| 570 | |
| 571 | if ((dev->bus->secondary == 0x0) && |
| 572 | (dev->path.pci.devfn == 0x0)) |
| 573 | *root_level = depth; |
| 574 | |
| 575 | if ((*root_level != -1) && (dev->enabled)) { |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 576 | if (depth != *root_level) |
| 577 | ivrs_add_device_or_bridge(parent, dev, current, ivhd_length); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 578 | } |
| 579 | } |
| 580 | |
| 581 | for (link = dev->link_list; link; link = link->next) |
| 582 | for (sibling = link->children; sibling; sibling = |
| 583 | sibling->sibling) |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 584 | add_ivhd_device_entries(dev, sibling, depth + 1, depth, root_level, |
| 585 | current, ivhd_length); |
| 586 | |
| 587 | free(root_level); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 588 | } |
| 589 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 590 | #define IOMMU_MMIO32(x) (*((volatile uint32_t *)(x))) |
| 591 | #define EFR_SUPPORT BIT(27) |
| 592 | |
| 593 | static unsigned long acpi_fill_ivrs11(unsigned long current, acpi_ivrs_t *ivrs_agesa) |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 594 | { |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 595 | acpi_ivrs_ivhd11_t *ivhd_11; |
| 596 | unsigned long current_backup; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 597 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 598 | /* |
| 599 | * These devices should be already found by previous function. |
| 600 | * Do not perform NULL checks. |
| 601 | */ |
| 602 | struct device *nb_dev = pcidev_on_root(0, 0); |
| 603 | struct device *iommu_dev = pcidev_on_root(0, 2); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 604 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 605 | /* |
| 606 | * In order to utilize all features, firmware should expose type 11h |
| 607 | * IVHD which supersedes the type 10h. |
| 608 | */ |
| 609 | memset((void *)current, 0, sizeof(acpi_ivrs_ivhd11_t)); |
| 610 | ivhd_11 = (acpi_ivrs_ivhd11_t *)current; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 611 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 612 | /* Enable EFR */ |
| 613 | ivhd_11->type = IVHD_BLOCK_TYPE_FULL__FIXED; |
| 614 | /* For type 11h bits 6 and 7 are reserved */ |
| 615 | ivhd_11->flags = ivrs_agesa->ivhd.flags & 0x3f; |
| 616 | ivhd_11->length = sizeof(struct acpi_ivrs_ivhd_11); |
| 617 | /* BDF <bus>:00.2 */ |
| 618 | ivhd_11->device_id = 0x02 | (nb_dev->bus->secondary << 8); |
| 619 | /* PCI Capability block 0x40 (type 0xf, "Secure device") */ |
| 620 | ivhd_11->capability_offset = 0x40; |
| 621 | ivhd_11->iommu_base_low = ivrs_agesa->ivhd.iommu_base_low; |
| 622 | ivhd_11->iommu_base_high = ivrs_agesa->ivhd.iommu_base_high; |
| 623 | ivhd_11->pci_segment_group = 0x0000; |
| 624 | ivhd_11->iommu_info = ivrs_agesa->ivhd.iommu_info; |
| 625 | ivhd_11->iommu_attributes.perf_counters = |
| 626 | (IOMMU_MMIO32(ivhd_11->iommu_base_low + 0x4000) >> 7) & 0xf; |
| 627 | ivhd_11->iommu_attributes.perf_counter_banks = |
| 628 | (IOMMU_MMIO32(ivhd_11->iommu_base_low + 0x4000) >> 12) & 0x3f; |
| 629 | ivhd_11->iommu_attributes.msi_num_ppr = |
| 630 | (pci_read_config32(iommu_dev, ivhd_11->capability_offset + 0x10) >> 27) & 0x1f; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 631 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 632 | if (pci_read_config32(iommu_dev, ivhd_11->capability_offset) & EFR_SUPPORT) { |
| 633 | ivhd_11->efr_reg_image_low = IOMMU_MMIO32(ivhd_11->iommu_base_low + 0x30); |
| 634 | ivhd_11->efr_reg_image_high = IOMMU_MMIO32(ivhd_11->iommu_base_low + 0x34); |
| 635 | } |
| 636 | |
| 637 | current += sizeof(acpi_ivrs_ivhd11_t); |
| 638 | |
| 639 | /* Now repeat all the device entries from type 10h */ |
| 640 | current_backup = current; |
| 641 | current = ivhd_dev_range(current, PCI_DEVFN(1, 0), PCI_DEVFN(0x1f, 6), 0); |
| 642 | ivhd_11->length += (current - current_backup); |
| 643 | add_ivhd_device_entries(NULL, all_devices, 0, -1, NULL, ¤t, &ivhd_11->length); |
| 644 | |
| 645 | /* Describe HPET */ |
| 646 | current_backup = current; |
| 647 | current = ivhd_describe_hpet(current); |
| 648 | ivhd_11->length += (current - current_backup); |
| 649 | |
| 650 | /* Describe IOAPICs */ |
| 651 | current_backup = current; |
| 652 | current = acpi_fill_ivrs_ioapic(ivrs_agesa, current); |
| 653 | ivhd_11->length += (current - current_backup); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 654 | |
| 655 | return current; |
| 656 | } |
| 657 | |
| 658 | static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current) |
| 659 | { |
Piotr Król | 063e156 | 2018-07-22 20:52:26 +0200 | [diff] [blame] | 660 | acpi_ivrs_t *ivrs_agesa; |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 661 | unsigned long current_backup; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 662 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 663 | struct device *nb_dev = pcidev_on_root(0, 0); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 664 | if (!nb_dev) { |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 665 | printk(BIOS_WARNING, "%s: G-series northbridge device not present!\n", __func__); |
| 666 | printk(BIOS_WARNING, "%s: IVRS table not generated...\n", __func__); |
| 667 | |
| 668 | return (unsigned long)ivrs; |
| 669 | } |
| 670 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 671 | struct device *iommu_dev = pcidev_on_root(0, 2); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 672 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 673 | if (!iommu_dev) { |
| 674 | printk(BIOS_WARNING, "%s: IOMMU device not found\n", __func__); |
| 675 | |
| 676 | return (unsigned long)ivrs; |
| 677 | } |
| 678 | |
Piotr Król | 063e156 | 2018-07-22 20:52:26 +0200 | [diff] [blame] | 679 | ivrs_agesa = agesawrapper_getlateinitptr(PICK_IVRS); |
| 680 | if (ivrs_agesa != NULL) { |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 681 | ivrs->iv_info = ivrs_agesa->iv_info; |
| 682 | ivrs->ivhd.type = IVHD_BLOCK_TYPE_LEGACY__FIXED; |
| 683 | ivrs->ivhd.flags = ivrs_agesa->ivhd.flags; |
Piotr Król | 063e156 | 2018-07-22 20:52:26 +0200 | [diff] [blame] | 684 | ivrs->ivhd.length = sizeof(struct acpi_ivrs_ivhd); |
| 685 | /* BDF <bus>:00.2 */ |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 686 | ivrs->ivhd.device_id = 0x02 | (nb_dev->bus->secondary << 8); |
| 687 | /* PCI Capability block 0x40 (type 0xf, "Secure device") */ |
Piotr Król | 063e156 | 2018-07-22 20:52:26 +0200 | [diff] [blame] | 688 | ivrs->ivhd.capability_offset = 0x40; |
| 689 | ivrs->ivhd.iommu_base_low = ivrs_agesa->ivhd.iommu_base_low; |
| 690 | ivrs->ivhd.iommu_base_high = ivrs_agesa->ivhd.iommu_base_high; |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 691 | ivrs->ivhd.pci_segment_group = 0x0000; |
| 692 | ivrs->ivhd.iommu_info = ivrs_agesa->ivhd.iommu_info; |
| 693 | ivrs->ivhd.iommu_feature_info = ivrs_agesa->ivhd.iommu_feature_info; |
| 694 | /* Enable EFR if supported */ |
| 695 | if (pci_read_config32(iommu_dev, ivrs->ivhd.capability_offset) & EFR_SUPPORT) |
| 696 | ivrs->iv_info |= IVINFO_EFR_SUPPORTED; |
Piotr Król | 063e156 | 2018-07-22 20:52:26 +0200 | [diff] [blame] | 697 | } else { |
| 698 | printk(BIOS_WARNING, "%s: AGESA returned NULL IVRS\n", __func__); |
| 699 | |
| 700 | return (unsigned long)ivrs; |
| 701 | } |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 702 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 703 | /* |
| 704 | * Add all possible PCI devices on bus 0 that can generate transactions |
| 705 | * processed by IOMMU. Start with device 00:01.0 since IOMMU does not |
| 706 | * translate transactions generated by itself. |
| 707 | */ |
| 708 | current_backup = current; |
| 709 | current = ivhd_dev_range(current, PCI_DEVFN(1, 0), PCI_DEVFN(0x1f, 6), 0); |
| 710 | ivrs->ivhd.length += (current - current_backup); |
| 711 | add_ivhd_device_entries(NULL, all_devices, 0, -1, NULL, ¤t, &ivrs->ivhd.length); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 712 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 713 | /* Describe HPET */ |
| 714 | current_backup = current; |
| 715 | current = ivhd_describe_hpet(current); |
| 716 | ivrs->ivhd.length += (current - current_backup); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 717 | |
| 718 | /* Describe IOAPICs */ |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 719 | current_backup = current; |
| 720 | current = acpi_fill_ivrs_ioapic(ivrs_agesa, current); |
| 721 | ivrs->ivhd.length += (current - current_backup); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 722 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 723 | /* If EFR is not supported, IVHD type 11h is reserved */ |
| 724 | if (!(ivrs->iv_info & IVINFO_EFR_SUPPORTED)) |
| 725 | return current; |
| 726 | |
| 727 | return acpi_fill_ivrs11(current, ivrs_agesa); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 728 | } |
| 729 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 730 | static void northbridge_fill_ssdt_generator(struct device *device) |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 731 | { |
| 732 | msr_t msr; |
| 733 | char pscope[] = "\\_SB.PCI0"; |
| 734 | |
| 735 | acpigen_write_scope(pscope); |
| 736 | msr = rdmsr(TOP_MEM); |
| 737 | acpigen_write_name_dword("TOM1", msr.lo); |
| 738 | msr = rdmsr(TOP_MEM2); |
| 739 | /* |
| 740 | * Since XP only implements parts of ACPI 2.0, we can't use a qword |
| 741 | * here. |
| 742 | * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt |
| 743 | * slide 22ff. |
| 744 | * Shift value right by 20 bit to make it fit into 32bit, |
| 745 | * giving us 1MB granularity and a limit of almost 4Exabyte of memory. |
| 746 | */ |
| 747 | acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); |
| 748 | acpigen_pop_len(); |
| 749 | } |
| 750 | |
Michał Żygowski | 9550e97 | 2020-03-20 13:56:46 +0100 | [diff] [blame] | 751 | static void patch_ssdt_processor_scope(acpi_header_t *ssdt) |
| 752 | { |
| 753 | unsigned int len = ssdt->length - sizeof(acpi_header_t); |
| 754 | unsigned int i; |
| 755 | |
| 756 | for (i = sizeof(acpi_header_t); i < len; i++) { |
| 757 | /* Search for _PR_ scope and replace it with _SB_ */ |
| 758 | if (*(uint32_t *)((unsigned long)ssdt + i) == 0x5f52505f) |
| 759 | *(uint32_t *)((unsigned long)ssdt + i) = 0x5f42535f; |
| 760 | } |
| 761 | /* Recalculate checksum */ |
| 762 | ssdt->checksum = 0; |
| 763 | ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length); |
| 764 | } |
| 765 | |
Furquan Shaikh | 0f007d8 | 2020-04-24 06:41:18 -0700 | [diff] [blame] | 766 | static unsigned long agesa_write_acpi_tables(const struct device *device, |
Alexander Couzens | 83fc32f | 2015-04-12 22:28:37 +0200 | [diff] [blame] | 767 | unsigned long current, |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 768 | acpi_rsdp_t *rsdp) |
| 769 | { |
| 770 | acpi_srat_t *srat; |
| 771 | acpi_slit_t *slit; |
| 772 | acpi_header_t *ssdt; |
| 773 | acpi_header_t *alib; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 774 | acpi_ivrs_t *ivrs; |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 775 | |
| 776 | /* HEST */ |
| 777 | current = ALIGN(current, 8); |
Vladimir Serbinenko | 807127f | 2014-11-09 13:36:18 +0100 | [diff] [blame] | 778 | acpi_write_hest((void *)current, acpi_fill_hest); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 779 | acpi_add_table(rsdp, (void *)current); |
| 780 | current += ((acpi_header_t *)current)->length; |
| 781 | |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 782 | /* IVRS */ |
| 783 | current = ALIGN(current, 8); |
| 784 | printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); |
| 785 | ivrs = (acpi_ivrs_t *) current; |
| 786 | acpi_create_ivrs(ivrs, acpi_fill_ivrs); |
| 787 | current += ivrs->header.length; |
| 788 | acpi_add_table(rsdp, ivrs); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 789 | |
| 790 | /* SRAT */ |
| 791 | current = ALIGN(current, 8); |
| 792 | printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); |
| 793 | srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); |
| 794 | if (srat != NULL) { |
| 795 | memcpy((void *)current, srat, srat->header.length); |
| 796 | srat = (acpi_srat_t *) current; |
| 797 | current += srat->header.length; |
| 798 | acpi_add_table(rsdp, srat); |
| 799 | } else { |
| 800 | printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n"); |
| 801 | } |
| 802 | |
| 803 | /* SLIT */ |
| 804 | current = ALIGN(current, 8); |
| 805 | printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); |
| 806 | slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); |
| 807 | if (slit != NULL) { |
| 808 | memcpy((void *)current, slit, slit->header.length); |
| 809 | slit = (acpi_slit_t *) current; |
| 810 | current += slit->header.length; |
| 811 | acpi_add_table(rsdp, slit); |
| 812 | } else { |
| 813 | printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n"); |
| 814 | } |
| 815 | |
| 816 | /* ALIB */ |
| 817 | current = ALIGN(current, 16); |
| 818 | printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); |
| 819 | alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); |
| 820 | if (alib != NULL) { |
| 821 | memcpy((void *)current, alib, alib->length); |
| 822 | alib = (acpi_header_t *) current; |
| 823 | current += alib->length; |
| 824 | acpi_add_table(rsdp, (void *)alib); |
| 825 | } |
| 826 | else { |
| 827 | printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); |
| 828 | } |
| 829 | |
| 830 | /* this pstate ssdt may cause Blue Screen: Fixed: Keep this comment for a while. */ |
| 831 | /* SSDT */ |
| 832 | current = ALIGN(current, 16); |
| 833 | printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); |
| 834 | ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); |
| 835 | if (ssdt != NULL) { |
Michał Żygowski | 9550e97 | 2020-03-20 13:56:46 +0100 | [diff] [blame] | 836 | patch_ssdt_processor_scope(ssdt); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 837 | memcpy((void *)current, ssdt, ssdt->length); |
| 838 | ssdt = (acpi_header_t *) current; |
| 839 | current += ssdt->length; |
| 840 | } |
| 841 | else { |
| 842 | printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n"); |
| 843 | } |
| 844 | acpi_add_table(rsdp,ssdt); |
| 845 | |
| 846 | printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); |
| 847 | return current; |
| 848 | } |
| 849 | |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 850 | static struct device_operations northbridge_operations = { |
| 851 | .read_resources = read_resources, |
| 852 | .set_resources = set_resources, |
| 853 | .enable_resources = pci_dev_enable_resources, |
| 854 | .init = northbridge_init, |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 855 | .acpi_fill_ssdt = northbridge_fill_ssdt_generator, |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 856 | .write_acpi_tables = agesa_write_acpi_tables, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 857 | }; |
| 858 | |
| 859 | static const struct pci_driver family16_northbridge __pci_driver = { |
| 860 | .ops = &northbridge_operations, |
| 861 | .vendor = PCI_VENDOR_ID_AMD, |
Marshall Dawson | 463f46e | 2016-10-14 20:46:08 -0600 | [diff] [blame] | 862 | .device = PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_HT, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 863 | }; |
| 864 | |
| 865 | static const struct pci_driver family10_northbridge __pci_driver = { |
| 866 | .ops = &northbridge_operations, |
| 867 | .vendor = PCI_VENDOR_ID_AMD, |
| 868 | .device = PCI_DEVICE_ID_AMD_10H_NB_HT, |
| 869 | }; |
| 870 | |
Dave Frodin | 891f71a | 2015-01-19 15:58:24 -0700 | [diff] [blame] | 871 | static void fam16_finalize(void *chip_info) |
| 872 | { |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 873 | struct device *dev; |
Dave Frodin | 891f71a | 2015-01-19 15:58:24 -0700 | [diff] [blame] | 874 | u32 value; |
Kyösti Mälkki | 33ff44c | 2018-05-22 01:15:22 +0300 | [diff] [blame] | 875 | dev = pcidev_on_root(0, 0); /* clear IoapicSbFeatureEn */ |
Dave Frodin | 891f71a | 2015-01-19 15:58:24 -0700 | [diff] [blame] | 876 | pci_write_config32(dev, 0xF8, 0); |
| 877 | pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ |
| 878 | |
Michał Żygowski | 6ca5b47 | 2019-09-10 15:10:22 +0200 | [diff] [blame] | 879 | /* |
| 880 | * Currently it is impossible to enable ACS with AGESA by setting the |
| 881 | * correct bit for AmdInitMid phase. AGESA code path does not call the |
| 882 | * right function that enables these functionalities. Disabled ACS |
| 883 | * result in multiple PCIe devices to be assigned to the same IOMMU |
| 884 | * group. Without IOMMU group separation the devices cannot be passed |
| 885 | * through independently. |
| 886 | */ |
| 887 | |
| 888 | /* Select GPP link core IO Link Strap Control register 0xB0 */ |
| 889 | pci_write_config32(dev, 0xE0, 0x014000B0); |
| 890 | value = pci_read_config32(dev, 0xE4); |
| 891 | |
| 892 | /* Enable AER (bit 5) and ACS (bit 6 undocumented) */ |
| 893 | value |= PCIE_CAP_AER | PCIE_CAP_ACS; |
| 894 | pci_write_config32(dev, 0xE4, value); |
| 895 | |
| 896 | /* Select GPP link core Wrapper register 0x00 (undocumented) */ |
| 897 | pci_write_config32(dev, 0xE0, 0x01300000); |
| 898 | value = pci_read_config32(dev, 0xE4); |
| 899 | |
| 900 | /* |
| 901 | * Enable ACS capabilities straps including sub-items. From lspci it |
| 902 | * looks like these bits enable: Source Validation and Translation |
| 903 | * Blocking |
| 904 | */ |
| 905 | value |= (BIT(24) | BIT(25) | BIT(26)); |
| 906 | pci_write_config32(dev, 0xE4, value); |
| 907 | |
Dave Frodin | 891f71a | 2015-01-19 15:58:24 -0700 | [diff] [blame] | 908 | /* disable No Snoop */ |
Kyösti Mälkki | 33ff44c | 2018-05-22 01:15:22 +0300 | [diff] [blame] | 909 | dev = pcidev_on_root(1, 1); |
Kyösti Mälkki | 69f6fd4 | 2019-01-21 14:19:01 +0200 | [diff] [blame] | 910 | if (dev != NULL) { |
| 911 | value = pci_read_config32(dev, 0x60); |
| 912 | value &= ~(1 << 11); |
| 913 | pci_write_config32(dev, 0x60, value); |
| 914 | } |
Dave Frodin | 891f71a | 2015-01-19 15:58:24 -0700 | [diff] [blame] | 915 | } |
| 916 | |
Kyösti Mälkki | e4c17ce | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 917 | struct chip_operations northbridge_amd_pi_00730F01_ops = { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 918 | CHIP_NAME("AMD FAM16 Northbridge") |
| 919 | .enable_dev = 0, |
Dave Frodin | 891f71a | 2015-01-19 15:58:24 -0700 | [diff] [blame] | 920 | .final = fam16_finalize, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 921 | }; |
| 922 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 923 | static void domain_read_resources(struct device *dev) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 924 | { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 925 | unsigned int reg; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 926 | |
| 927 | /* Find the already assigned resource pairs */ |
| 928 | get_fx_devs(); |
| 929 | for (reg = 0x80; reg <= 0xd8; reg+= 0x08) { |
| 930 | u32 base, limit; |
| 931 | base = f1_read_config32(reg); |
| 932 | limit = f1_read_config32(reg + 0x04); |
| 933 | /* Is this register allocated? */ |
| 934 | if ((base & 3) != 0) { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 935 | unsigned int nodeid, reg_link; |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 936 | struct device *reg_dev; |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 937 | if (reg < 0xc0) { // mmio |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 938 | nodeid = (limit & 0xf) + (base&0x30); |
| 939 | } else { // io |
| 940 | nodeid = (limit & 0xf) + ((base>>4)&0x30); |
| 941 | } |
| 942 | reg_link = (limit >> 4) & 7; |
| 943 | reg_dev = __f0_dev[nodeid]; |
| 944 | if (reg_dev) { |
| 945 | /* Reserve the resource */ |
| 946 | struct resource *res; |
| 947 | res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link)); |
| 948 | if (res) { |
| 949 | res->flags = 1; |
| 950 | } |
| 951 | } |
| 952 | } |
| 953 | } |
| 954 | /* FIXME: do we need to check extend conf space? |
| 955 | I don't believe that much preset value */ |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 956 | pci_domain_read_resources(dev); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 957 | } |
| 958 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 959 | static void domain_enable_resources(struct device *dev) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 960 | { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 961 | } |
| 962 | |
| 963 | #if CONFIG_HW_MEM_HOLE_SIZEK != 0 |
| 964 | struct hw_mem_hole_info { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 965 | unsigned int hole_startk; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 966 | int node_id; |
| 967 | }; |
| 968 | static struct hw_mem_hole_info get_hw_mem_hole_info(void) |
| 969 | { |
| 970 | struct hw_mem_hole_info mem_hole; |
| 971 | int i; |
| 972 | mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; |
| 973 | mem_hole.node_id = -1; |
| 974 | for (i = 0; i < node_nums; i++) { |
| 975 | dram_base_mask_t d; |
| 976 | u32 hole; |
| 977 | d = get_dram_base_mask(i); |
| 978 | if (!(d.mask & 1)) continue; // no memory on this node |
| 979 | hole = pci_read_config32(__f1_dev[i], 0xf0); |
| 980 | if (hole & 2) { // we find the hole |
| 981 | mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; |
| 982 | mem_hole.node_id = i; // record the node No with hole |
| 983 | break; // only one hole |
| 984 | } |
| 985 | } |
| 986 | |
| 987 | /* We need to double check if there is special set on base reg and limit reg |
| 988 | * are not continuous instead of hole, it will find out its hole_startk. |
| 989 | */ |
| 990 | if (mem_hole.node_id == -1) { |
| 991 | resource_t limitk_pri = 0; |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 992 | for (i = 0; i < node_nums; i++) { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 993 | dram_base_mask_t d; |
| 994 | resource_t base_k, limit_k; |
| 995 | d = get_dram_base_mask(i); |
| 996 | if (!(d.base & 1)) continue; |
| 997 | base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; |
| 998 | if (base_k > 4 *1024 * 1024) break; // don't need to go to check |
| 999 | if (limitk_pri != base_k) { // we find the hole |
Elyes HAOUAS | 38a4f2a9 | 2020-01-07 19:53:36 +0100 | [diff] [blame] | 1000 | mem_hole.hole_startk = (unsigned int)limitk_pri; // must be below 4G |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1001 | mem_hole.node_id = i; |
| 1002 | break; //only one hole |
| 1003 | } |
| 1004 | limit_k = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; |
| 1005 | limitk_pri = limit_k; |
| 1006 | } |
| 1007 | } |
| 1008 | return mem_hole; |
| 1009 | } |
| 1010 | #endif |
| 1011 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 1012 | static void domain_set_resources(struct device *dev) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1013 | { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1014 | unsigned long mmio_basek; |
| 1015 | u32 pci_tolm; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1016 | int i, idx; |
| 1017 | struct bus *link; |
| 1018 | #if CONFIG_HW_MEM_HOLE_SIZEK != 0 |
| 1019 | struct hw_mem_hole_info mem_hole; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1020 | #endif |
| 1021 | |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1022 | pci_tolm = 0xffffffffUL; |
| 1023 | for (link = dev->link_list; link; link = link->next) { |
| 1024 | pci_tolm = find_pci_tolm(link); |
| 1025 | } |
| 1026 | |
| 1027 | // FIXME handle interleaved nodes. If you fix this here, please fix |
| 1028 | // amdk8, too. |
| 1029 | mmio_basek = pci_tolm >> 10; |
| 1030 | /* Round mmio_basek to something the processor can support */ |
| 1031 | mmio_basek &= ~((1 << 6) -1); |
| 1032 | |
| 1033 | // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M |
| 1034 | // MMIO hole. If you fix this here, please fix amdk8, too. |
| 1035 | /* Round the mmio hole to 64M */ |
| 1036 | mmio_basek &= ~((64*1024) - 1); |
| 1037 | |
| 1038 | #if CONFIG_HW_MEM_HOLE_SIZEK != 0 |
| 1039 | /* if the hw mem hole is already set in raminit stage, here we will compare |
| 1040 | * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will |
| 1041 | * use hole_basek as mmio_basek and we don't need to reset hole. |
| 1042 | * otherwise We reset the hole to the mmio_basek |
| 1043 | */ |
| 1044 | |
| 1045 | mem_hole = get_hw_mem_hole_info(); |
| 1046 | |
| 1047 | // Use hole_basek as mmio_basek, and we don't need to reset hole anymore |
| 1048 | if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { |
| 1049 | mmio_basek = mem_hole.hole_startk; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1050 | } |
| 1051 | #endif |
| 1052 | |
| 1053 | idx = 0x10; |
| 1054 | for (i = 0; i < node_nums; i++) { |
| 1055 | dram_base_mask_t d; |
| 1056 | resource_t basek, limitk, sizek; // 4 1T |
| 1057 | |
| 1058 | d = get_dram_base_mask(i); |
| 1059 | |
| 1060 | if (!(d.mask & 1)) continue; |
| 1061 | basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here |
Elyes HAOUAS | 7db506c | 2016-10-02 11:56:39 +0200 | [diff] [blame] | 1062 | limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1063 | |
| 1064 | sizek = limitk - basek; |
| 1065 | |
| 1066 | /* see if we need a hole from 0xa0000 to 0xbffff */ |
| 1067 | if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) { |
| 1068 | ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek); |
| 1069 | idx += 0x10; |
| 1070 | basek = (8*64)+(16*16); |
| 1071 | sizek = limitk - ((8*64)+(16*16)); |
| 1072 | |
| 1073 | } |
| 1074 | |
| 1075 | //printk(BIOS_DEBUG, "node %d : mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", i, mmio_basek, basek, limitk); |
| 1076 | |
| 1077 | /* split the region to accommodate pci memory space */ |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 1078 | if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1079 | if (basek <= mmio_basek) { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 1080 | unsigned int pre_sizek; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1081 | pre_sizek = mmio_basek - basek; |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 1082 | if (pre_sizek > 0) { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1083 | ram_resource(dev, (idx | i), basek, pre_sizek); |
| 1084 | idx += 0x10; |
| 1085 | sizek -= pre_sizek; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1086 | } |
| 1087 | basek = mmio_basek; |
| 1088 | } |
| 1089 | if ((basek + sizek) <= 4*1024*1024) { |
| 1090 | sizek = 0; |
| 1091 | } |
| 1092 | else { |
| 1093 | uint64_t topmem2 = bsp_topmem2(); |
| 1094 | basek = 4*1024*1024; |
| 1095 | sizek = topmem2/1024 - basek; |
| 1096 | } |
| 1097 | } |
| 1098 | |
| 1099 | ram_resource(dev, (idx | i), basek, sizek); |
| 1100 | idx += 0x10; |
| 1101 | printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", |
| 1102 | i, mmio_basek, basek, limitk); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1103 | } |
| 1104 | |
Kyösti Mälkki | e87564f | 2017-04-15 20:07:53 +0300 | [diff] [blame] | 1105 | add_uma_resource_below_tolm(dev, 7); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1106 | |
Elyes HAOUAS | 5a7e72f | 2016-08-23 21:36:02 +0200 | [diff] [blame] | 1107 | for (link = dev->link_list; link; link = link->next) { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1108 | if (link->children) { |
| 1109 | assign_resources(link); |
| 1110 | } |
| 1111 | } |
| 1112 | } |
| 1113 | |
Aaron Durbin | aa090cb | 2017-09-13 16:01:52 -0600 | [diff] [blame] | 1114 | static const char *domain_acpi_name(const struct device *dev) |
Philipp Deppenwiese | 3067012 | 2017-03-01 02:24:33 +0100 | [diff] [blame] | 1115 | { |
| 1116 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 1117 | return "PCI0"; |
| 1118 | |
| 1119 | return NULL; |
| 1120 | } |
| 1121 | |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1122 | static struct device_operations pci_domain_ops = { |
| 1123 | .read_resources = domain_read_resources, |
| 1124 | .set_resources = domain_set_resources, |
| 1125 | .enable_resources = domain_enable_resources, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1126 | .scan_bus = pci_domain_scan_bus, |
Philipp Deppenwiese | 3067012 | 2017-03-01 02:24:33 +0100 | [diff] [blame] | 1127 | .acpi_name = domain_acpi_name, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1128 | }; |
| 1129 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 1130 | static void sysconf_init(struct device *dev) // first node |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1131 | { |
| 1132 | sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 |
| 1133 | node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; //NodeCnt[2:0] |
| 1134 | } |
| 1135 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 1136 | static void cpu_bus_scan(struct device *dev) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1137 | { |
| 1138 | struct bus *cpu_bus; |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 1139 | struct device *dev_mc; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1140 | int i,j; |
| 1141 | int coreid_bits; |
| 1142 | int core_max = 0; |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 1143 | unsigned int ApicIdCoreIdSize; |
| 1144 | unsigned int core_nums; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1145 | int siblings = 0; |
| 1146 | unsigned int family; |
| 1147 | u32 modules = 0; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1148 | int ioapic_count = 0; |
| 1149 | |
Michał Żygowski | e719288 | 2019-11-23 19:02:19 +0100 | [diff] [blame] | 1150 | /* For binaryPI there is no multiprocessor configuration, the number of |
| 1151 | * modules will always be 1. */ |
| 1152 | modules = 1; |
| 1153 | ioapic_count = CONFIG_NUM_OF_IOAPICS; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1154 | |
Kyösti Mälkki | bbd2377 | 2019-01-10 05:41:23 +0200 | [diff] [blame] | 1155 | dev_mc = pcidev_on_root(DEV_CDB, 0); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1156 | if (!dev_mc) { |
Kyösti Mälkki | bbd2377 | 2019-01-10 05:41:23 +0200 | [diff] [blame] | 1157 | printk(BIOS_ERR, "0:%02x.0 not found", DEV_CDB); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1158 | die(""); |
| 1159 | } |
| 1160 | sysconf_init(dev_mc); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1161 | |
| 1162 | /* Get Max Number of cores(MNC) */ |
Kyösti Mälkki | d41feed | 2017-09-24 16:23:57 +0300 | [diff] [blame] | 1163 | coreid_bits = (cpuid_ecx(0x80000008) & 0x0000F000) >> 12; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1164 | core_max = 1 << (coreid_bits & 0x000F); //mnc |
| 1165 | |
| 1166 | ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF); |
| 1167 | if (ApicIdCoreIdSize) { |
| 1168 | core_nums = (1 << ApicIdCoreIdSize) - 1; |
| 1169 | } else { |
| 1170 | core_nums = 3; //quad core |
| 1171 | } |
| 1172 | |
| 1173 | /* Find which cpus are present */ |
| 1174 | cpu_bus = dev->link_list; |
| 1175 | for (i = 0; i < node_nums; i++) { |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 1176 | struct device *cdb_dev; |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 1177 | unsigned int devn; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1178 | struct bus *pbus; |
| 1179 | |
Kyösti Mälkki | bbd2377 | 2019-01-10 05:41:23 +0200 | [diff] [blame] | 1180 | devn = DEV_CDB + i; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1181 | pbus = dev_mc->bus; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1182 | |
| 1183 | /* Find the cpu's pci device */ |
Kyösti Mälkki | 33ff44c | 2018-05-22 01:15:22 +0300 | [diff] [blame] | 1184 | cdb_dev = pcidev_on_root(devn, 0); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1185 | if (!cdb_dev) { |
| 1186 | /* If I am probing things in a weird order |
| 1187 | * ensure all of the cpu's pci devices are found. |
| 1188 | */ |
| 1189 | int fn; |
Elyes HAOUAS | 5a7e72f | 2016-08-23 21:36:02 +0200 | [diff] [blame] | 1190 | for (fn = 0; fn <= 5; fn++) { //FBDIMM? |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1191 | cdb_dev = pci_probe_dev(NULL, pbus, |
| 1192 | PCI_DEVFN(devn, fn)); |
| 1193 | } |
Kyösti Mälkki | 33ff44c | 2018-05-22 01:15:22 +0300 | [diff] [blame] | 1194 | cdb_dev = pcidev_on_root(devn, 0); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1195 | } else { |
| 1196 | /* Ok, We need to set the links for that device. |
| 1197 | * otherwise the device under it will not be scanned |
| 1198 | */ |
Kyösti Mälkki | c5163ed8 | 2015-02-04 13:25:37 +0200 | [diff] [blame] | 1199 | |
| 1200 | add_more_links(cdb_dev, 4); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1201 | } |
| 1202 | |
| 1203 | family = cpuid_eax(1); |
| 1204 | family = (family >> 20) & 0xFF; |
| 1205 | if (family == 1) { //f10 |
| 1206 | u32 dword; |
Kyösti Mälkki | 33ff44c | 2018-05-22 01:15:22 +0300 | [diff] [blame] | 1207 | cdb_dev = pcidev_on_root(devn, 3); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1208 | dword = pci_read_config32(cdb_dev, 0xe8); |
| 1209 | siblings = ((dword & BIT15) >> 13) | ((dword & (BIT13 | BIT12)) >> 12); |
| 1210 | } else if (family == 7) {//f16 |
Kyösti Mälkki | 33ff44c | 2018-05-22 01:15:22 +0300 | [diff] [blame] | 1211 | cdb_dev = pcidev_on_root(devn, 5); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1212 | if (cdb_dev && cdb_dev->enabled) { |
| 1213 | siblings = pci_read_config32(cdb_dev, 0x84); |
| 1214 | siblings &= 0xFF; |
| 1215 | } |
| 1216 | } else { |
| 1217 | siblings = 0; //default one core |
| 1218 | } |
| 1219 | int enable_node = cdb_dev && cdb_dev->enabled; |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 1220 | printk(BIOS_SPEW, "%s family%xh, core_max = 0x%x, core_nums = 0x%x, siblings = 0x%x\n", |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1221 | dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); |
| 1222 | |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 1223 | for (j = 0; j <= siblings; j++) { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1224 | u32 lapicid_start = 0; |
| 1225 | |
| 1226 | /* |
Elyes HAOUAS | 38a4f2a9 | 2020-01-07 19:53:36 +0100 | [diff] [blame] | 1227 | * APIC ID calculation is tightly coupled with AGESA v5 code. |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1228 | * This calculation MUST match the assignment calculation done |
| 1229 | * in LocalApicInitializationAtEarly() function. |
| 1230 | * And reference GetLocalApicIdForCore() |
| 1231 | * |
Elyes HAOUAS | a5b0bc4 | 2020-02-20 20:04:29 +0100 | [diff] [blame] | 1232 | * Apply APIC enumeration rules |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1233 | * For systems with >= 16 APICs, put the IO-APICs at 0..n and |
| 1234 | * put the local-APICs at m..z |
| 1235 | * |
| 1236 | * This is needed because many IO-APIC devices only have 4 bits |
| 1237 | * for their APIC id and therefore must reside at 0..15 |
Elyes HAOUAS | 6e8b3c1 | 2016-09-02 19:22:00 +0200 | [diff] [blame] | 1238 | */ |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1239 | if ((node_nums * core_max) + ioapic_count >= 0x10) { |
| 1240 | lapicid_start = (ioapic_count - 1) / core_max; |
| 1241 | lapicid_start = (lapicid_start + 1) * core_max; |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 1242 | printk(BIOS_SPEW, "lpaicid_start = 0x%x ", lapicid_start); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1243 | } |
| 1244 | u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 1245 | printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n", |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1246 | i, j, apic_id); |
| 1247 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 1248 | struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1249 | if (cpu) |
| 1250 | amd_cpu_topology(cpu, i, j); |
| 1251 | } //j |
| 1252 | } |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1253 | } |
| 1254 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 1255 | static void cpu_bus_init(struct device *dev) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1256 | { |
| 1257 | initialize_cpus(dev->link_list); |
| 1258 | } |
| 1259 | |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1260 | static struct device_operations cpu_bus_ops = { |
Nico Huber | 2f8ba69 | 2020-04-05 14:05:24 +0200 | [diff] [blame] | 1261 | .read_resources = noop_read_resources, |
| 1262 | .set_resources = noop_set_resources, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1263 | .init = cpu_bus_init, |
| 1264 | .scan_bus = cpu_bus_scan, |
| 1265 | }; |
| 1266 | |
| 1267 | static void root_complex_enable_dev(struct device *dev) |
| 1268 | { |
| 1269 | static int done = 0; |
| 1270 | |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1271 | if (!done) { |
| 1272 | setup_bsp_ramtop(); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1273 | done = 1; |
| 1274 | } |
| 1275 | |
| 1276 | /* Set the operations if it is a special bus type */ |
| 1277 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
| 1278 | dev->ops = &pci_domain_ops; |
| 1279 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
| 1280 | dev->ops = &cpu_bus_ops; |
| 1281 | } |
| 1282 | } |
| 1283 | |
Kyösti Mälkki | e4c17ce | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 1284 | struct chip_operations northbridge_amd_pi_00730F01_root_complex_ops = { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 1285 | CHIP_NAME("AMD FAM16 Root Complex") |
| 1286 | .enable_dev = root_complex_enable_dev, |
| 1287 | }; |
| 1288 | |
| 1289 | /********************************************************************* |
| 1290 | * Change the vendor / device IDs to match the generic VBIOS header. * |
| 1291 | *********************************************************************/ |
| 1292 | u32 map_oprom_vendev(u32 vendev) |
| 1293 | { |
| 1294 | u32 new_vendev; |
| 1295 | new_vendev = |
| 1296 | ((0x10029850 <= vendev) && (vendev <= 0x1002986F)) ? 0x10029850 : vendev; |
| 1297 | |
| 1298 | if (vendev != new_vendev) |
| 1299 | printk(BIOS_NOTICE, "Mapping PCI device %8x to %8x\n", vendev, new_vendev); |
| 1300 | |
| 1301 | return new_vendev; |
| 1302 | } |