Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <stdint.h> |
| 22 | #include <string.h> |
| 23 | #include <lib.h> |
| 24 | #include <timestamp.h> |
| 25 | #include <arch/io.h> |
Stefan Reinauer | 11a20b6 | 2012-11-29 15:19:43 -0800 | [diff] [blame] | 26 | #include <arch/byteorder.h> |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 27 | #include <device/pci_def.h> |
| 28 | #include <device/pnp_def.h> |
| 29 | #include <cpu/x86/lapic.h> |
| 30 | #include <pc80/mc146818rtc.h> |
| 31 | #include <cbfs.h> |
Kyösti Mälkki | 6722f8d | 2014-06-16 09:14:49 +0300 | [diff] [blame] | 32 | #include <arch/acpi.h> |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 33 | #include <cbmem.h> |
| 34 | #include <console/console.h> |
Kyösti Mälkki | e3ddee0 | 2014-05-03 10:45:28 +0300 | [diff] [blame] | 35 | #include <bootmode.h> |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 36 | #include "northbridge/intel/sandybridge/sandybridge.h" |
| 37 | #include "northbridge/intel/sandybridge/raminit.h" |
| 38 | #include "southbridge/intel/bd82x6x/pch.h" |
| 39 | #include "southbridge/intel/bd82x6x/gpio.h" |
| 40 | #include <arch/cpu.h> |
| 41 | #include <cpu/x86/bist.h> |
| 42 | #include <cpu/x86/msr.h> |
Patrick Georgi | bd79c5e | 2014-11-28 22:35:36 +0100 | [diff] [blame] | 43 | #include <halt.h> |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 44 | #include "option_table.h" |
| 45 | #include "gpio.h" |
Kyösti Mälkki | afa7b13 | 2014-02-13 17:16:22 +0200 | [diff] [blame] | 46 | #if CONFIG_DRIVERS_UART_8250IO |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 47 | #include "superio/smsc/lpc47n207/lpc47n207.h" |
| 48 | #include "superio/smsc/lpc47n207/early_serial.c" |
| 49 | #endif |
| 50 | #if CONFIG_CHROMEOS |
| 51 | #include <vendorcode/google/chromeos/chromeos.h> |
| 52 | #endif |
| 53 | |
| 54 | static void pch_enable_lpc(void) |
| 55 | { |
| 56 | /* Set COM1/COM2 decode range */ |
| 57 | pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); |
| 58 | |
Kyösti Mälkki | afa7b13 | 2014-02-13 17:16:22 +0200 | [diff] [blame] | 59 | #if CONFIG_DRIVERS_UART_8250IO |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 60 | /* Enable SuperIO + EC + KBC + COM1 + lpc47n207 config*/ |
| 61 | pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN | |
| 62 | KBC_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN); |
| 63 | |
| 64 | /* map full 256 bytes at 0x1600 to the LPC bus */ |
| 65 | pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0xfc1601); |
| 66 | |
| 67 | try_enabling_LPC47N207_uart(); |
| 68 | #else |
| 69 | /* Enable SuperIO + EC + KBC */ |
| 70 | pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN | |
| 71 | KBC_LPC_EN); |
| 72 | #endif |
| 73 | } |
| 74 | |
| 75 | static void rcba_config(void) |
| 76 | { |
| 77 | u32 reg32; |
| 78 | |
Vladimir Serbinenko | 33b535f | 2014-10-19 10:13:14 +0200 | [diff] [blame] | 79 | southbridge_configure_default_intmap(); |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 80 | |
| 81 | /* Enable IOAPIC (generic) */ |
| 82 | RCBA16(OIC) = 0x0100; |
| 83 | /* PCH BWG says to read back the IOAPIC enable register */ |
| 84 | (void) RCBA16(OIC); |
| 85 | |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 86 | /* Disable unused devices (board specific) */ |
| 87 | reg32 = RCBA32(FD); |
| 88 | reg32 |= PCH_DISABLE_ALWAYS; |
| 89 | RCBA32(FD) = reg32; |
| 90 | } |
| 91 | |
| 92 | static void early_pch_init(void) |
| 93 | { |
| 94 | u8 reg8; |
| 95 | |
| 96 | // reset rtc power status |
| 97 | reg8 = pci_read_config8(PCH_LPC_DEV, 0xa4); |
| 98 | reg8 &= ~(1 << 2); |
| 99 | pci_write_config8(PCH_LPC_DEV, 0xa4, reg8); |
| 100 | } |
| 101 | |
Aaron Durbin | a0a3727 | 2014-08-14 08:35:11 -0500 | [diff] [blame] | 102 | #include <cpu/intel/romstage.h> |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 103 | void main(unsigned long bist) |
| 104 | { |
| 105 | int boot_mode = 0; |
| 106 | int cbmem_was_initted; |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 107 | |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 108 | struct pei_data pei_data = { |
Edward O'Callaghan | c9714bc | 2014-10-29 06:16:51 +1100 | [diff] [blame] | 109 | .pei_version = PEI_VERSION, |
| 110 | .mchbar = DEFAULT_MCHBAR, |
| 111 | .dmibar = DEFAULT_DMIBAR, |
| 112 | .epbar = DEFAULT_EPBAR, |
| 113 | .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, |
| 114 | .smbusbar = SMBUS_IO_BASE, |
| 115 | .wdbbar = 0x4000000, |
| 116 | .wdbsize = 0x1000, |
| 117 | .hpet_address = CONFIG_HPET_ADDRESS, |
| 118 | .rcba = DEFAULT_RCBABASE, |
| 119 | .pmbase = DEFAULT_PMBASE, |
| 120 | .gpiobase = DEFAULT_GPIOBASE, |
| 121 | .thermalbase = 0xfed08000, |
| 122 | .system_type = 0, // 0 Mobile, 1 Desktop/Server |
| 123 | .tseg_size = CONFIG_SMM_TSEG_SIZE, |
| 124 | .spd_addresses = { 0xa0, 0x00,0x00,0x00 }, |
| 125 | .ts_addresses = { 0x30, 0x00, 0x00, 0x00 }, |
| 126 | .ec_present = 1, |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 127 | // 0 = leave channel enabled |
| 128 | // 1 = disable dimm 0 on channel |
| 129 | // 2 = disable dimm 1 on channel |
| 130 | // 3 = disable dimm 0+1 on channel |
Edward O'Callaghan | c9714bc | 2014-10-29 06:16:51 +1100 | [diff] [blame] | 131 | .dimm_channel0_disabled = 2, |
| 132 | .dimm_channel1_disabled = 2, |
| 133 | .max_ddr3_freq = 1333, |
| 134 | .usb_port_config = { |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 135 | { 1, 0, 0x0080 }, /* P0: Port 0 (OC0) */ |
| 136 | { 1, 1, 0x0080 }, /* P1: Port 1 (OC1) */ |
| 137 | { 1, 0, 0x0040 }, /* P2: MINIPCIE1 (no OC) */ |
| 138 | { 1, 0, 0x0040 }, /* P3: MMC (no OC) */ |
| 139 | { 0, 0, 0x0000 }, /* P4: Empty */ |
| 140 | { 0, 0, 0x0000 }, /* P5: Empty */ |
| 141 | { 0, 0, 0x0000 }, /* P6: Empty */ |
| 142 | { 0, 0, 0x0000 }, /* P7: Empty */ |
| 143 | { 1, 4, 0x0040 }, /* P8: MINIPCIE2 (no OC) */ |
| 144 | { 0, 4, 0x0000 }, /* P9: Empty */ |
| 145 | { 0, 4, 0x0000 }, /* P10: Empty */ |
| 146 | { 1, 4, 0x0040 }, /* P11: Camera (no OC) */ |
| 147 | { 0, 4, 0x0000 }, /* P12: Empty */ |
| 148 | { 0, 4, 0x0000 }, /* P13: Empty */ |
| 149 | }, |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 150 | }; |
| 151 | |
| 152 | typedef const uint8_t spd_blob[256]; |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 153 | spd_blob *spd_data; |
Vladimir Serbinenko | 1287416 | 2014-01-12 14:12:15 +0100 | [diff] [blame] | 154 | size_t spd_file_len; |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 155 | |
| 156 | |
Kyösti Mälkki | 3d45c40 | 2013-09-07 20:26:36 +0300 | [diff] [blame] | 157 | timestamp_init(get_initial_timestamp()); |
| 158 | timestamp_add_now(TS_START_ROMSTAGE); |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 159 | |
| 160 | if (bist == 0) |
| 161 | enable_lapic(); |
| 162 | |
| 163 | pch_enable_lpc(); |
| 164 | |
| 165 | /* Enable GPIOs */ |
| 166 | pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); |
| 167 | pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); |
| 168 | setup_pch_gpios(&lumpy_gpio_map); |
| 169 | |
| 170 | console_init(); |
| 171 | |
Kyösti Mälkki | e3ddee0 | 2014-05-03 10:45:28 +0300 | [diff] [blame] | 172 | init_bootmode_straps(); |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 173 | |
| 174 | /* Halt if there was a built in self test failure */ |
| 175 | report_bist_failure(bist); |
| 176 | |
| 177 | if (MCHBAR16(SSKPD) == 0xCAFE) { |
| 178 | printk(BIOS_DEBUG, "soft reset detected\n"); |
| 179 | boot_mode = 1; |
| 180 | |
| 181 | /* System is not happy after keyboard reset... */ |
| 182 | printk(BIOS_DEBUG, "Issuing CF9 warm reset\n"); |
| 183 | outb(0x6, 0xcf9); |
Patrick Georgi | bd79c5e | 2014-11-28 22:35:36 +0100 | [diff] [blame] | 184 | halt(); |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 185 | } |
| 186 | |
| 187 | /* Perform some early chipset initialization required |
| 188 | * before RAM initialization can work |
| 189 | */ |
| 190 | sandybridge_early_initialization(SANDYBRIDGE_MOBILE); |
| 191 | printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); |
| 192 | |
Vladimir Serbinenko | 332f14b | 2014-09-05 16:29:41 +0200 | [diff] [blame] | 193 | boot_mode = southbridge_detect_s3_resume() ? 2 : 0; |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 194 | |
| 195 | post_code(0x38); |
| 196 | /* Enable SPD ROMs and DDR-III DRAM */ |
| 197 | enable_smbus(); |
| 198 | |
| 199 | /* Prepare USB controller early in S3 resume */ |
| 200 | if (boot_mode == 2) |
| 201 | enable_usb_bar(); |
| 202 | |
| 203 | u32 gp_lvl2 = inl(DEFAULT_GPIOBASE + 0x38); |
| 204 | u8 gpio33, gpio41, gpio49; |
| 205 | gpio33 = (gp_lvl2 >> (33-32)) & 1; |
| 206 | gpio41 = (gp_lvl2 >> (41-32)) & 1; |
| 207 | gpio49 = (gp_lvl2 >> (49-32)) & 1; |
| 208 | printk(BIOS_DEBUG, "Memory Straps:\n"); |
| 209 | printk(BIOS_DEBUG, " - memory capacity %dGB\n", |
| 210 | gpio33 ? 2 : 1); |
| 211 | printk(BIOS_DEBUG, " - die revision %d\n", |
| 212 | gpio41 ? 2 : 1); |
| 213 | printk(BIOS_DEBUG, " - vendor %s\n", |
| 214 | gpio49 ? "Samsung" : "Other"); |
| 215 | |
| 216 | int spd_index = 0; |
| 217 | |
| 218 | switch ((gpio49 << 2) | (gpio41 << 1) | gpio33) { |
| 219 | case 0: // Other 1G Rev 1 |
| 220 | spd_index = 0; |
| 221 | break; |
| 222 | case 2: // Other 1G Rev 2 |
| 223 | spd_index = 1; |
| 224 | break; |
| 225 | case 1: // Other 2G Rev 1 |
| 226 | case 3: // Other 2G Rev 2 |
| 227 | spd_index = 2; |
| 228 | break; |
| 229 | case 4: // Samsung 1G Rev 1 |
| 230 | spd_index = 3; |
| 231 | break; |
| 232 | case 6: // Samsung 1G Rev 2 |
| 233 | spd_index = 4; |
| 234 | break; |
| 235 | case 5: // Samsung 2G Rev 1 |
| 236 | case 7: // Samsung 2G Rev 2 |
| 237 | spd_index = 5; |
| 238 | break; |
| 239 | } |
| 240 | |
Vladimir Serbinenko | 1287416 | 2014-01-12 14:12:15 +0100 | [diff] [blame] | 241 | spd_data = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", 0xab, |
| 242 | &spd_file_len); |
| 243 | if (!spd_data) |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 244 | die("SPD data not found."); |
Vladimir Serbinenko | 1287416 | 2014-01-12 14:12:15 +0100 | [diff] [blame] | 245 | if (spd_file_len < (spd_index + 1) * 256) |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 246 | die("Missing SPD data."); |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 247 | // leave onboard dimm address at f0, and copy spd data there. |
| 248 | memcpy(pei_data.spd_data[0], spd_data[spd_index], 256); |
| 249 | |
| 250 | post_code(0x39); |
| 251 | pei_data.boot_mode = boot_mode; |
Kyösti Mälkki | 3d45c40 | 2013-09-07 20:26:36 +0300 | [diff] [blame] | 252 | timestamp_add_now(TS_BEFORE_INITRAM); |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 253 | sdram_initialize(&pei_data); |
| 254 | |
Kyösti Mälkki | 3d45c40 | 2013-09-07 20:26:36 +0300 | [diff] [blame] | 255 | timestamp_add_now(TS_AFTER_INITRAM); |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 256 | post_code(0x3a); |
| 257 | /* Perform some initialization that must run before stage2 */ |
| 258 | early_pch_init(); |
| 259 | post_code(0x3b); |
| 260 | |
| 261 | rcba_config(); |
| 262 | post_code(0x3c); |
| 263 | |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 264 | quick_ram_check(); |
Stefan Reinauer | afcaac2 | 2012-06-18 15:43:50 -0700 | [diff] [blame] | 265 | post_code(0x3e); |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 266 | |
Kyösti Mälkki | 2d8520b | 2014-01-06 17:20:31 +0200 | [diff] [blame] | 267 | cbmem_was_initted = !cbmem_recovery(boot_mode==2); |
Kyösti Mälkki | 7893848 | 2014-01-04 11:02:45 +0200 | [diff] [blame] | 268 | if (boot_mode!=2) |
| 269 | save_mrc_data(&pei_data); |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 270 | |
Vladimir Serbinenko | c845b43 | 2014-09-05 03:37:44 +0200 | [diff] [blame] | 271 | if (boot_mode == 2 && !cbmem_was_initted) { |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 272 | /* Failed S3 resume, reset to come up cleanly */ |
| 273 | outb(0x6, 0xcf9); |
Patrick Georgi | bd79c5e | 2014-11-28 22:35:36 +0100 | [diff] [blame] | 274 | halt(); |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 275 | } |
Vladimir Serbinenko | c845b43 | 2014-09-05 03:37:44 +0200 | [diff] [blame] | 276 | northbridge_romstage_finalize(boot_mode==2); |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 277 | post_code(0x3f); |
| 278 | #if CONFIG_CHROMEOS |
| 279 | init_chromeos(boot_mode); |
| 280 | #endif |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 281 | timestamp_add_now(TS_END_ROMSTAGE); |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 282 | } |