Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <stdint.h> |
| 22 | #include <string.h> |
| 23 | #include <lib.h> |
| 24 | #include <timestamp.h> |
| 25 | #include <arch/io.h> |
Stefan Reinauer | 11a20b6 | 2012-11-29 15:19:43 -0800 | [diff] [blame] | 26 | #include <arch/byteorder.h> |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 27 | #include <device/pci_def.h> |
| 28 | #include <device/pnp_def.h> |
| 29 | #include <cpu/x86/lapic.h> |
| 30 | #include <pc80/mc146818rtc.h> |
| 31 | #include <cbfs.h> |
Kyösti Mälkki | 6722f8d | 2014-06-16 09:14:49 +0300 | [diff] [blame^] | 32 | #include <arch/acpi.h> |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 33 | #include <cbmem.h> |
| 34 | #include <console/console.h> |
Kyösti Mälkki | e3ddee0 | 2014-05-03 10:45:28 +0300 | [diff] [blame] | 35 | #include <bootmode.h> |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 36 | #include "northbridge/intel/sandybridge/sandybridge.h" |
| 37 | #include "northbridge/intel/sandybridge/raminit.h" |
| 38 | #include "southbridge/intel/bd82x6x/pch.h" |
| 39 | #include "southbridge/intel/bd82x6x/gpio.h" |
| 40 | #include <arch/cpu.h> |
| 41 | #include <cpu/x86/bist.h> |
| 42 | #include <cpu/x86/msr.h> |
| 43 | #include "option_table.h" |
| 44 | #include "gpio.h" |
Kyösti Mälkki | afa7b13 | 2014-02-13 17:16:22 +0200 | [diff] [blame] | 45 | #if CONFIG_DRIVERS_UART_8250IO |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 46 | #include "superio/smsc/lpc47n207/lpc47n207.h" |
| 47 | #include "superio/smsc/lpc47n207/early_serial.c" |
| 48 | #endif |
| 49 | #if CONFIG_CHROMEOS |
| 50 | #include <vendorcode/google/chromeos/chromeos.h> |
| 51 | #endif |
| 52 | |
| 53 | static void pch_enable_lpc(void) |
| 54 | { |
| 55 | /* Set COM1/COM2 decode range */ |
| 56 | pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); |
| 57 | |
Kyösti Mälkki | afa7b13 | 2014-02-13 17:16:22 +0200 | [diff] [blame] | 58 | #if CONFIG_DRIVERS_UART_8250IO |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 59 | /* Enable SuperIO + EC + KBC + COM1 + lpc47n207 config*/ |
| 60 | pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN | |
| 61 | KBC_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN); |
| 62 | |
| 63 | /* map full 256 bytes at 0x1600 to the LPC bus */ |
| 64 | pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0xfc1601); |
| 65 | |
| 66 | try_enabling_LPC47N207_uart(); |
| 67 | #else |
| 68 | /* Enable SuperIO + EC + KBC */ |
| 69 | pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN | |
| 70 | KBC_LPC_EN); |
| 71 | #endif |
| 72 | } |
| 73 | |
| 74 | static void rcba_config(void) |
| 75 | { |
| 76 | u32 reg32; |
| 77 | |
| 78 | /* |
| 79 | * GFX INTA -> PIRQA (MSI) |
| 80 | * D28IP_P1IP WLAN INTA -> PIRQB |
| 81 | * D28IP_P4IP ETH0 INTB -> PIRQC (MSI) |
| 82 | * D29IP_E1P EHCI1 INTA -> PIRQD |
| 83 | * D26IP_E2P EHCI2 INTA -> PIRQB |
| 84 | * D31IP_SIP SATA INTA -> PIRQA (MSI) |
| 85 | * D31IP_SMIP SMBUS INTC -> PIRQH |
| 86 | * D31IP_TTIP THRT INTB -> PIRQG |
| 87 | * D27IP_ZIP HDA INTA -> PIRQG (MSI) |
| 88 | * |
| 89 | * LIGHTSENSOR -> PIRQE (Edge Triggered) |
| 90 | * TRACKPAD -> PIRQF (Edge Triggered) |
| 91 | */ |
| 92 | |
| 93 | /* Device interrupt pin register (board specific) */ |
| 94 | RCBA32(D31IP) = (INTB << D31IP_TTIP) | (NOINT << D31IP_SIP2) | |
| 95 | (INTC << D31IP_SMIP) | (INTA << D31IP_SIP); |
| 96 | RCBA32(D30IP) = (NOINT << D30IP_PIP); |
| 97 | RCBA32(D29IP) = (INTA << D29IP_E1P); |
| 98 | RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | |
| 99 | (INTB << D28IP_P4IP); |
| 100 | RCBA32(D27IP) = (INTA << D27IP_ZIP); |
| 101 | RCBA32(D26IP) = (INTA << D26IP_E2P); |
| 102 | RCBA32(D25IP) = (NOINT << D25IP_LIP); |
| 103 | RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); |
| 104 | |
| 105 | /* Device interrupt route registers */ |
| 106 | DIR_ROUTE(D31IR, PIRQA, PIRQG, PIRQH, PIRQB); |
| 107 | DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQG, PIRQH); |
| 108 | DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); |
| 109 | DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB); |
| 110 | DIR_ROUTE(D26IR, PIRQB, PIRQC, PIRQD, PIRQA); |
| 111 | DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); |
| 112 | DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); |
| 113 | |
| 114 | /* Enable IOAPIC (generic) */ |
| 115 | RCBA16(OIC) = 0x0100; |
| 116 | /* PCH BWG says to read back the IOAPIC enable register */ |
| 117 | (void) RCBA16(OIC); |
| 118 | |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 119 | /* Disable unused devices (board specific) */ |
| 120 | reg32 = RCBA32(FD); |
| 121 | reg32 |= PCH_DISABLE_ALWAYS; |
| 122 | RCBA32(FD) = reg32; |
| 123 | } |
| 124 | |
| 125 | static void early_pch_init(void) |
| 126 | { |
| 127 | u8 reg8; |
| 128 | |
| 129 | // reset rtc power status |
| 130 | reg8 = pci_read_config8(PCH_LPC_DEV, 0xa4); |
| 131 | reg8 &= ~(1 << 2); |
| 132 | pci_write_config8(PCH_LPC_DEV, 0xa4, reg8); |
| 133 | } |
| 134 | |
| 135 | void main(unsigned long bist) |
| 136 | { |
| 137 | int boot_mode = 0; |
| 138 | int cbmem_was_initted; |
| 139 | u32 pm1_cnt; |
| 140 | u16 pm1_sts; |
| 141 | |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 142 | struct pei_data pei_data = { |
Stefan Reinauer | dedcc78 | 2013-07-29 14:02:06 -0700 | [diff] [blame] | 143 | pei_version: PEI_VERSION, |
| 144 | mchbar: DEFAULT_MCHBAR, |
| 145 | dmibar: DEFAULT_DMIBAR, |
| 146 | epbar: DEFAULT_EPBAR, |
| 147 | pciexbar: CONFIG_MMCONF_BASE_ADDRESS, |
| 148 | smbusbar: SMBUS_IO_BASE, |
| 149 | wdbbar: 0x4000000, |
| 150 | wdbsize: 0x1000, |
| 151 | hpet_address: CONFIG_HPET_ADDRESS, |
| 152 | rcba: DEFAULT_RCBABASE, |
| 153 | pmbase: DEFAULT_PMBASE, |
| 154 | gpiobase: DEFAULT_GPIOBASE, |
| 155 | thermalbase: 0xfed08000, |
| 156 | system_type: 0, // 0 Mobile, 1 Desktop/Server |
| 157 | tseg_size: CONFIG_SMM_TSEG_SIZE, |
| 158 | spd_addresses: { 0xa0, 0x00,0x00,0x00 }, |
| 159 | ts_addresses: { 0x30, 0x00, 0x00, 0x00 }, |
| 160 | ec_present: 1, |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 161 | // 0 = leave channel enabled |
| 162 | // 1 = disable dimm 0 on channel |
| 163 | // 2 = disable dimm 1 on channel |
| 164 | // 3 = disable dimm 0+1 on channel |
Stefan Reinauer | dedcc78 | 2013-07-29 14:02:06 -0700 | [diff] [blame] | 165 | dimm_channel0_disabled: 2, |
| 166 | dimm_channel1_disabled: 2, |
| 167 | max_ddr3_freq: 1333, |
| 168 | usb_port_config: { |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 169 | { 1, 0, 0x0080 }, /* P0: Port 0 (OC0) */ |
| 170 | { 1, 1, 0x0080 }, /* P1: Port 1 (OC1) */ |
| 171 | { 1, 0, 0x0040 }, /* P2: MINIPCIE1 (no OC) */ |
| 172 | { 1, 0, 0x0040 }, /* P3: MMC (no OC) */ |
| 173 | { 0, 0, 0x0000 }, /* P4: Empty */ |
| 174 | { 0, 0, 0x0000 }, /* P5: Empty */ |
| 175 | { 0, 0, 0x0000 }, /* P6: Empty */ |
| 176 | { 0, 0, 0x0000 }, /* P7: Empty */ |
| 177 | { 1, 4, 0x0040 }, /* P8: MINIPCIE2 (no OC) */ |
| 178 | { 0, 4, 0x0000 }, /* P9: Empty */ |
| 179 | { 0, 4, 0x0000 }, /* P10: Empty */ |
| 180 | { 1, 4, 0x0040 }, /* P11: Camera (no OC) */ |
| 181 | { 0, 4, 0x0000 }, /* P12: Empty */ |
| 182 | { 0, 4, 0x0000 }, /* P13: Empty */ |
| 183 | }, |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 184 | }; |
| 185 | |
| 186 | typedef const uint8_t spd_blob[256]; |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 187 | spd_blob *spd_data; |
Vladimir Serbinenko | 1287416 | 2014-01-12 14:12:15 +0100 | [diff] [blame] | 188 | size_t spd_file_len; |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 189 | |
| 190 | |
Kyösti Mälkki | 3d45c40 | 2013-09-07 20:26:36 +0300 | [diff] [blame] | 191 | timestamp_init(get_initial_timestamp()); |
| 192 | timestamp_add_now(TS_START_ROMSTAGE); |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 193 | |
| 194 | if (bist == 0) |
| 195 | enable_lapic(); |
| 196 | |
| 197 | pch_enable_lpc(); |
| 198 | |
| 199 | /* Enable GPIOs */ |
| 200 | pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); |
| 201 | pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); |
| 202 | setup_pch_gpios(&lumpy_gpio_map); |
| 203 | |
| 204 | console_init(); |
| 205 | |
Kyösti Mälkki | e3ddee0 | 2014-05-03 10:45:28 +0300 | [diff] [blame] | 206 | init_bootmode_straps(); |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 207 | |
| 208 | /* Halt if there was a built in self test failure */ |
| 209 | report_bist_failure(bist); |
| 210 | |
| 211 | if (MCHBAR16(SSKPD) == 0xCAFE) { |
| 212 | printk(BIOS_DEBUG, "soft reset detected\n"); |
| 213 | boot_mode = 1; |
| 214 | |
| 215 | /* System is not happy after keyboard reset... */ |
| 216 | printk(BIOS_DEBUG, "Issuing CF9 warm reset\n"); |
| 217 | outb(0x6, 0xcf9); |
| 218 | hlt(); |
| 219 | } |
| 220 | |
| 221 | /* Perform some early chipset initialization required |
| 222 | * before RAM initialization can work |
| 223 | */ |
| 224 | sandybridge_early_initialization(SANDYBRIDGE_MOBILE); |
| 225 | printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); |
| 226 | |
| 227 | /* Check PM1_STS[15] to see if we are waking from Sx */ |
| 228 | pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); |
| 229 | |
| 230 | /* Read PM1_CNT[12:10] to determine which Sx state */ |
| 231 | pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); |
| 232 | |
| 233 | if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { |
Kyösti Mälkki | 6722f8d | 2014-06-16 09:14:49 +0300 | [diff] [blame^] | 234 | if (acpi_s3_resume_allowed()) { |
| 235 | printk(BIOS_DEBUG, "Resume from S3 detected.\n"); |
| 236 | boot_mode = 2; |
| 237 | /* Clear SLP_TYPE. This will break stage2 but |
| 238 | * we care for that when we get there. |
| 239 | */ |
| 240 | outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); |
| 241 | } else { |
| 242 | printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); |
| 243 | } |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 244 | } |
| 245 | |
| 246 | post_code(0x38); |
| 247 | /* Enable SPD ROMs and DDR-III DRAM */ |
| 248 | enable_smbus(); |
| 249 | |
| 250 | /* Prepare USB controller early in S3 resume */ |
| 251 | if (boot_mode == 2) |
| 252 | enable_usb_bar(); |
| 253 | |
| 254 | u32 gp_lvl2 = inl(DEFAULT_GPIOBASE + 0x38); |
| 255 | u8 gpio33, gpio41, gpio49; |
| 256 | gpio33 = (gp_lvl2 >> (33-32)) & 1; |
| 257 | gpio41 = (gp_lvl2 >> (41-32)) & 1; |
| 258 | gpio49 = (gp_lvl2 >> (49-32)) & 1; |
| 259 | printk(BIOS_DEBUG, "Memory Straps:\n"); |
| 260 | printk(BIOS_DEBUG, " - memory capacity %dGB\n", |
| 261 | gpio33 ? 2 : 1); |
| 262 | printk(BIOS_DEBUG, " - die revision %d\n", |
| 263 | gpio41 ? 2 : 1); |
| 264 | printk(BIOS_DEBUG, " - vendor %s\n", |
| 265 | gpio49 ? "Samsung" : "Other"); |
| 266 | |
| 267 | int spd_index = 0; |
| 268 | |
| 269 | switch ((gpio49 << 2) | (gpio41 << 1) | gpio33) { |
| 270 | case 0: // Other 1G Rev 1 |
| 271 | spd_index = 0; |
| 272 | break; |
| 273 | case 2: // Other 1G Rev 2 |
| 274 | spd_index = 1; |
| 275 | break; |
| 276 | case 1: // Other 2G Rev 1 |
| 277 | case 3: // Other 2G Rev 2 |
| 278 | spd_index = 2; |
| 279 | break; |
| 280 | case 4: // Samsung 1G Rev 1 |
| 281 | spd_index = 3; |
| 282 | break; |
| 283 | case 6: // Samsung 1G Rev 2 |
| 284 | spd_index = 4; |
| 285 | break; |
| 286 | case 5: // Samsung 2G Rev 1 |
| 287 | case 7: // Samsung 2G Rev 2 |
| 288 | spd_index = 5; |
| 289 | break; |
| 290 | } |
| 291 | |
Vladimir Serbinenko | 1287416 | 2014-01-12 14:12:15 +0100 | [diff] [blame] | 292 | spd_data = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", 0xab, |
| 293 | &spd_file_len); |
| 294 | if (!spd_data) |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 295 | die("SPD data not found."); |
Vladimir Serbinenko | 1287416 | 2014-01-12 14:12:15 +0100 | [diff] [blame] | 296 | if (spd_file_len < (spd_index + 1) * 256) |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 297 | die("Missing SPD data."); |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 298 | // leave onboard dimm address at f0, and copy spd data there. |
| 299 | memcpy(pei_data.spd_data[0], spd_data[spd_index], 256); |
| 300 | |
| 301 | post_code(0x39); |
| 302 | pei_data.boot_mode = boot_mode; |
Kyösti Mälkki | 3d45c40 | 2013-09-07 20:26:36 +0300 | [diff] [blame] | 303 | timestamp_add_now(TS_BEFORE_INITRAM); |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 304 | sdram_initialize(&pei_data); |
| 305 | |
Kyösti Mälkki | 3d45c40 | 2013-09-07 20:26:36 +0300 | [diff] [blame] | 306 | timestamp_add_now(TS_AFTER_INITRAM); |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 307 | post_code(0x3a); |
| 308 | /* Perform some initialization that must run before stage2 */ |
| 309 | early_pch_init(); |
| 310 | post_code(0x3b); |
| 311 | |
| 312 | rcba_config(); |
| 313 | post_code(0x3c); |
| 314 | |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 315 | quick_ram_check(); |
Stefan Reinauer | afcaac2 | 2012-06-18 15:43:50 -0700 | [diff] [blame] | 316 | post_code(0x3e); |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 317 | |
| 318 | MCHBAR16(SSKPD) = 0xCAFE; |
| 319 | |
Kyösti Mälkki | 2d8520b | 2014-01-06 17:20:31 +0200 | [diff] [blame] | 320 | cbmem_was_initted = !cbmem_recovery(boot_mode==2); |
Kyösti Mälkki | 7893848 | 2014-01-04 11:02:45 +0200 | [diff] [blame] | 321 | if (boot_mode!=2) |
| 322 | save_mrc_data(&pei_data); |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 323 | |
| 324 | #if CONFIG_HAVE_ACPI_RESUME |
| 325 | /* If there is no high memory area, we didn't boot before, so |
| 326 | * this is not a resume. In that case we just create the cbmem toc. |
| 327 | */ |
| 328 | |
| 329 | *(u32 *)CBMEM_BOOT_MODE = 0; |
| 330 | *(u32 *)CBMEM_RESUME_BACKUP = 0; |
| 331 | |
| 332 | if ((boot_mode == 2) && cbmem_was_initted) { |
| 333 | void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); |
| 334 | if (resume_backup_memory) { |
| 335 | *(u32 *)CBMEM_BOOT_MODE = boot_mode; |
| 336 | *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; |
| 337 | } |
| 338 | /* Magic for S3 resume */ |
| 339 | pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); |
| 340 | } else if (boot_mode == 2) { |
| 341 | /* Failed S3 resume, reset to come up cleanly */ |
| 342 | outb(0x6, 0xcf9); |
| 343 | hlt(); |
| 344 | } else { |
| 345 | pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); |
| 346 | } |
| 347 | #endif |
| 348 | post_code(0x3f); |
| 349 | #if CONFIG_CHROMEOS |
| 350 | init_chromeos(boot_mode); |
| 351 | #endif |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 352 | timestamp_add_now(TS_END_ROMSTAGE); |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 353 | } |