Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <stdint.h> |
| 22 | #include <string.h> |
| 23 | #include <lib.h> |
| 24 | #include <timestamp.h> |
| 25 | #include <arch/io.h> |
| 26 | #include <arch/romcc_io.h> |
Stefan Reinauer | 11a20b6 | 2012-11-29 15:19:43 -0800 | [diff] [blame^] | 27 | #include <arch/byteorder.h> |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 28 | #include <device/pci_def.h> |
| 29 | #include <device/pnp_def.h> |
| 30 | #include <cpu/x86/lapic.h> |
| 31 | #include <pc80/mc146818rtc.h> |
| 32 | #include <cbfs.h> |
| 33 | #include <cbmem.h> |
| 34 | #include <console/console.h> |
| 35 | #include "northbridge/intel/sandybridge/sandybridge.h" |
| 36 | #include "northbridge/intel/sandybridge/raminit.h" |
| 37 | #include "southbridge/intel/bd82x6x/pch.h" |
| 38 | #include "southbridge/intel/bd82x6x/gpio.h" |
| 39 | #include <arch/cpu.h> |
| 40 | #include <cpu/x86/bist.h> |
| 41 | #include <cpu/x86/msr.h> |
| 42 | #include "option_table.h" |
| 43 | #include "gpio.h" |
| 44 | #if CONFIG_CONSOLE_SERIAL8250 |
| 45 | #include "superio/smsc/lpc47n207/lpc47n207.h" |
| 46 | #include "superio/smsc/lpc47n207/early_serial.c" |
| 47 | #endif |
| 48 | #if CONFIG_CHROMEOS |
| 49 | #include <vendorcode/google/chromeos/chromeos.h> |
| 50 | #endif |
| 51 | |
| 52 | static void pch_enable_lpc(void) |
| 53 | { |
| 54 | /* Set COM1/COM2 decode range */ |
| 55 | pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); |
| 56 | |
| 57 | #if CONFIG_CONSOLE_SERIAL8250 |
| 58 | /* Enable SuperIO + EC + KBC + COM1 + lpc47n207 config*/ |
| 59 | pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN | |
| 60 | KBC_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN); |
| 61 | |
| 62 | /* map full 256 bytes at 0x1600 to the LPC bus */ |
| 63 | pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0xfc1601); |
| 64 | |
| 65 | try_enabling_LPC47N207_uart(); |
| 66 | #else |
| 67 | /* Enable SuperIO + EC + KBC */ |
| 68 | pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN | |
| 69 | KBC_LPC_EN); |
| 70 | #endif |
| 71 | } |
| 72 | |
| 73 | static void rcba_config(void) |
| 74 | { |
| 75 | u32 reg32; |
| 76 | |
| 77 | /* |
| 78 | * GFX INTA -> PIRQA (MSI) |
| 79 | * D28IP_P1IP WLAN INTA -> PIRQB |
| 80 | * D28IP_P4IP ETH0 INTB -> PIRQC (MSI) |
| 81 | * D29IP_E1P EHCI1 INTA -> PIRQD |
| 82 | * D26IP_E2P EHCI2 INTA -> PIRQB |
| 83 | * D31IP_SIP SATA INTA -> PIRQA (MSI) |
| 84 | * D31IP_SMIP SMBUS INTC -> PIRQH |
| 85 | * D31IP_TTIP THRT INTB -> PIRQG |
| 86 | * D27IP_ZIP HDA INTA -> PIRQG (MSI) |
| 87 | * |
| 88 | * LIGHTSENSOR -> PIRQE (Edge Triggered) |
| 89 | * TRACKPAD -> PIRQF (Edge Triggered) |
| 90 | */ |
| 91 | |
| 92 | /* Device interrupt pin register (board specific) */ |
| 93 | RCBA32(D31IP) = (INTB << D31IP_TTIP) | (NOINT << D31IP_SIP2) | |
| 94 | (INTC << D31IP_SMIP) | (INTA << D31IP_SIP); |
| 95 | RCBA32(D30IP) = (NOINT << D30IP_PIP); |
| 96 | RCBA32(D29IP) = (INTA << D29IP_E1P); |
| 97 | RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | |
| 98 | (INTB << D28IP_P4IP); |
| 99 | RCBA32(D27IP) = (INTA << D27IP_ZIP); |
| 100 | RCBA32(D26IP) = (INTA << D26IP_E2P); |
| 101 | RCBA32(D25IP) = (NOINT << D25IP_LIP); |
| 102 | RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); |
| 103 | |
| 104 | /* Device interrupt route registers */ |
| 105 | DIR_ROUTE(D31IR, PIRQA, PIRQG, PIRQH, PIRQB); |
| 106 | DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQG, PIRQH); |
| 107 | DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); |
| 108 | DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB); |
| 109 | DIR_ROUTE(D26IR, PIRQB, PIRQC, PIRQD, PIRQA); |
| 110 | DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); |
| 111 | DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); |
| 112 | |
| 113 | /* Enable IOAPIC (generic) */ |
| 114 | RCBA16(OIC) = 0x0100; |
| 115 | /* PCH BWG says to read back the IOAPIC enable register */ |
| 116 | (void) RCBA16(OIC); |
| 117 | |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 118 | /* Disable unused devices (board specific) */ |
| 119 | reg32 = RCBA32(FD); |
| 120 | reg32 |= PCH_DISABLE_ALWAYS; |
| 121 | RCBA32(FD) = reg32; |
| 122 | } |
| 123 | |
| 124 | static void early_pch_init(void) |
| 125 | { |
| 126 | u8 reg8; |
| 127 | |
| 128 | // reset rtc power status |
| 129 | reg8 = pci_read_config8(PCH_LPC_DEV, 0xa4); |
| 130 | reg8 &= ~(1 << 2); |
| 131 | pci_write_config8(PCH_LPC_DEV, 0xa4, reg8); |
| 132 | } |
| 133 | |
| 134 | void main(unsigned long bist) |
| 135 | { |
| 136 | int boot_mode = 0; |
| 137 | int cbmem_was_initted; |
| 138 | u32 pm1_cnt; |
| 139 | u16 pm1_sts; |
| 140 | |
| 141 | #if CONFIG_COLLECT_TIMESTAMPS |
| 142 | tsc_t start_romstage_time; |
| 143 | tsc_t before_dram_time; |
| 144 | tsc_t after_dram_time; |
| 145 | tsc_t base_time = { |
| 146 | .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), |
| 147 | .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) |
| 148 | }; |
| 149 | #endif |
| 150 | |
| 151 | struct pei_data pei_data = { |
Stefan Reinauer | e6063fe | 2012-04-30 14:57:51 -0700 | [diff] [blame] | 152 | .mchbar = DEFAULT_MCHBAR, |
| 153 | .dmibar = DEFAULT_DMIBAR, |
| 154 | .epbar = DEFAULT_EPBAR, |
| 155 | .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, |
| 156 | .smbusbar = SMBUS_IO_BASE, |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 157 | .wdbbar = 0x4000000, |
| 158 | .wdbsize = 0x1000, |
Patrick Georgi | 9aeb694 | 2012-10-05 21:54:38 +0200 | [diff] [blame] | 159 | .hpet_address = CONFIG_HPET_ADDRESS, |
Stefan Reinauer | e6063fe | 2012-04-30 14:57:51 -0700 | [diff] [blame] | 160 | .rcba = DEFAULT_RCBABASE, |
| 161 | .pmbase = DEFAULT_PMBASE, |
| 162 | .gpiobase = DEFAULT_GPIOBASE, |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 163 | .thermalbase = 0xfed08000, |
| 164 | .system_type = 0, // 0 Mobile, 1 Desktop/Server |
| 165 | .tseg_size = CONFIG_SMM_TSEG_SIZE, |
| 166 | .spd_addresses = { 0x50, 0x00,0xf0,0x00 }, |
| 167 | .ts_addresses = { 0x30, 0x00, 0x00, 0x00 }, |
| 168 | .ec_present = 1, |
| 169 | // 0 = leave channel enabled |
| 170 | // 1 = disable dimm 0 on channel |
| 171 | // 2 = disable dimm 1 on channel |
| 172 | // 3 = disable dimm 0+1 on channel |
| 173 | .dimm_channel0_disabled = 2, |
| 174 | .dimm_channel1_disabled = 2, |
| 175 | .usb_port_config = { |
| 176 | { 1, 0, 0x0080 }, /* P0: Port 0 (OC0) */ |
| 177 | { 1, 1, 0x0080 }, /* P1: Port 1 (OC1) */ |
| 178 | { 1, 0, 0x0040 }, /* P2: MINIPCIE1 (no OC) */ |
| 179 | { 1, 0, 0x0040 }, /* P3: MMC (no OC) */ |
| 180 | { 0, 0, 0x0000 }, /* P4: Empty */ |
| 181 | { 0, 0, 0x0000 }, /* P5: Empty */ |
| 182 | { 0, 0, 0x0000 }, /* P6: Empty */ |
| 183 | { 0, 0, 0x0000 }, /* P7: Empty */ |
| 184 | { 1, 4, 0x0040 }, /* P8: MINIPCIE2 (no OC) */ |
| 185 | { 0, 4, 0x0000 }, /* P9: Empty */ |
| 186 | { 0, 4, 0x0000 }, /* P10: Empty */ |
| 187 | { 1, 4, 0x0040 }, /* P11: Camera (no OC) */ |
| 188 | { 0, 4, 0x0000 }, /* P12: Empty */ |
| 189 | { 0, 4, 0x0000 }, /* P13: Empty */ |
| 190 | }, |
| 191 | .spd_data = { |
| 192 | } |
| 193 | }; |
| 194 | |
| 195 | typedef const uint8_t spd_blob[256]; |
| 196 | struct cbfs_file *spd_file; |
| 197 | spd_blob *spd_data; |
| 198 | |
| 199 | |
| 200 | #if CONFIG_COLLECT_TIMESTAMPS |
| 201 | start_romstage_time = rdtsc(); |
| 202 | #endif |
| 203 | |
| 204 | if (bist == 0) |
| 205 | enable_lapic(); |
| 206 | |
| 207 | pch_enable_lpc(); |
| 208 | |
| 209 | /* Enable GPIOs */ |
| 210 | pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); |
| 211 | pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); |
| 212 | setup_pch_gpios(&lumpy_gpio_map); |
| 213 | |
| 214 | console_init(); |
| 215 | |
| 216 | #if CONFIG_CHROMEOS |
| 217 | save_chromeos_gpios(); |
| 218 | #endif |
| 219 | |
| 220 | /* Halt if there was a built in self test failure */ |
| 221 | report_bist_failure(bist); |
| 222 | |
| 223 | if (MCHBAR16(SSKPD) == 0xCAFE) { |
| 224 | printk(BIOS_DEBUG, "soft reset detected\n"); |
| 225 | boot_mode = 1; |
| 226 | |
| 227 | /* System is not happy after keyboard reset... */ |
| 228 | printk(BIOS_DEBUG, "Issuing CF9 warm reset\n"); |
| 229 | outb(0x6, 0xcf9); |
| 230 | hlt(); |
| 231 | } |
| 232 | |
| 233 | /* Perform some early chipset initialization required |
| 234 | * before RAM initialization can work |
| 235 | */ |
| 236 | sandybridge_early_initialization(SANDYBRIDGE_MOBILE); |
| 237 | printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); |
| 238 | |
| 239 | /* Check PM1_STS[15] to see if we are waking from Sx */ |
| 240 | pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); |
| 241 | |
| 242 | /* Read PM1_CNT[12:10] to determine which Sx state */ |
| 243 | pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); |
| 244 | |
| 245 | if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { |
| 246 | #if CONFIG_HAVE_ACPI_RESUME |
| 247 | printk(BIOS_DEBUG, "Resume from S3 detected.\n"); |
| 248 | boot_mode = 2; |
| 249 | /* Clear SLP_TYPE. This will break stage2 but |
| 250 | * we care for that when we get there. |
| 251 | */ |
| 252 | outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); |
| 253 | #else |
| 254 | printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); |
| 255 | #endif |
| 256 | } |
| 257 | |
| 258 | post_code(0x38); |
| 259 | /* Enable SPD ROMs and DDR-III DRAM */ |
| 260 | enable_smbus(); |
| 261 | |
| 262 | /* Prepare USB controller early in S3 resume */ |
| 263 | if (boot_mode == 2) |
| 264 | enable_usb_bar(); |
| 265 | |
| 266 | u32 gp_lvl2 = inl(DEFAULT_GPIOBASE + 0x38); |
| 267 | u8 gpio33, gpio41, gpio49; |
| 268 | gpio33 = (gp_lvl2 >> (33-32)) & 1; |
| 269 | gpio41 = (gp_lvl2 >> (41-32)) & 1; |
| 270 | gpio49 = (gp_lvl2 >> (49-32)) & 1; |
| 271 | printk(BIOS_DEBUG, "Memory Straps:\n"); |
| 272 | printk(BIOS_DEBUG, " - memory capacity %dGB\n", |
| 273 | gpio33 ? 2 : 1); |
| 274 | printk(BIOS_DEBUG, " - die revision %d\n", |
| 275 | gpio41 ? 2 : 1); |
| 276 | printk(BIOS_DEBUG, " - vendor %s\n", |
| 277 | gpio49 ? "Samsung" : "Other"); |
| 278 | |
| 279 | int spd_index = 0; |
| 280 | |
| 281 | switch ((gpio49 << 2) | (gpio41 << 1) | gpio33) { |
| 282 | case 0: // Other 1G Rev 1 |
| 283 | spd_index = 0; |
| 284 | break; |
| 285 | case 2: // Other 1G Rev 2 |
| 286 | spd_index = 1; |
| 287 | break; |
| 288 | case 1: // Other 2G Rev 1 |
| 289 | case 3: // Other 2G Rev 2 |
| 290 | spd_index = 2; |
| 291 | break; |
| 292 | case 4: // Samsung 1G Rev 1 |
| 293 | spd_index = 3; |
| 294 | break; |
| 295 | case 6: // Samsung 1G Rev 2 |
| 296 | spd_index = 4; |
| 297 | break; |
| 298 | case 5: // Samsung 2G Rev 1 |
| 299 | case 7: // Samsung 2G Rev 2 |
| 300 | spd_index = 5; |
| 301 | break; |
| 302 | } |
| 303 | |
| 304 | spd_file = cbfs_find("spd.bin"); |
| 305 | if (!spd_file) |
| 306 | die("SPD data not found."); |
| 307 | if (spd_file->len < (spd_index + 1) * 256) |
| 308 | die("Missing SPD data."); |
| 309 | spd_data = (spd_blob *)CBFS_SUBHEADER(spd_file); |
| 310 | // leave onboard dimm address at f0, and copy spd data there. |
| 311 | memcpy(pei_data.spd_data[0], spd_data[spd_index], 256); |
| 312 | |
| 313 | post_code(0x39); |
| 314 | pei_data.boot_mode = boot_mode; |
| 315 | #if CONFIG_COLLECT_TIMESTAMPS |
| 316 | before_dram_time = rdtsc(); |
| 317 | #endif |
| 318 | sdram_initialize(&pei_data); |
| 319 | |
| 320 | #if CONFIG_COLLECT_TIMESTAMPS |
| 321 | after_dram_time = rdtsc(); |
| 322 | #endif |
| 323 | post_code(0x3a); |
| 324 | /* Perform some initialization that must run before stage2 */ |
| 325 | early_pch_init(); |
| 326 | post_code(0x3b); |
| 327 | |
| 328 | rcba_config(); |
| 329 | post_code(0x3c); |
| 330 | |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 331 | quick_ram_check(); |
Stefan Reinauer | afcaac2 | 2012-06-18 15:43:50 -0700 | [diff] [blame] | 332 | post_code(0x3e); |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 333 | |
| 334 | MCHBAR16(SSKPD) = 0xCAFE; |
| 335 | |
| 336 | #if CONFIG_EARLY_CBMEM_INIT |
| 337 | cbmem_was_initted = !cbmem_initialize(); |
| 338 | #else |
| 339 | cbmem_was_initted = cbmem_reinit((uint64_t) (get_top_of_ram() |
| 340 | - HIGH_MEMORY_SIZE)); |
| 341 | #endif |
| 342 | |
| 343 | #if CONFIG_HAVE_ACPI_RESUME |
| 344 | /* If there is no high memory area, we didn't boot before, so |
| 345 | * this is not a resume. In that case we just create the cbmem toc. |
| 346 | */ |
| 347 | |
| 348 | *(u32 *)CBMEM_BOOT_MODE = 0; |
| 349 | *(u32 *)CBMEM_RESUME_BACKUP = 0; |
| 350 | |
| 351 | if ((boot_mode == 2) && cbmem_was_initted) { |
| 352 | void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); |
| 353 | if (resume_backup_memory) { |
| 354 | *(u32 *)CBMEM_BOOT_MODE = boot_mode; |
| 355 | *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; |
| 356 | } |
| 357 | /* Magic for S3 resume */ |
| 358 | pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); |
| 359 | } else if (boot_mode == 2) { |
| 360 | /* Failed S3 resume, reset to come up cleanly */ |
| 361 | outb(0x6, 0xcf9); |
| 362 | hlt(); |
| 363 | } else { |
| 364 | pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); |
| 365 | } |
| 366 | #endif |
| 367 | post_code(0x3f); |
| 368 | #if CONFIG_CHROMEOS |
| 369 | init_chromeos(boot_mode); |
| 370 | #endif |
| 371 | #if CONFIG_COLLECT_TIMESTAMPS |
| 372 | timestamp_init(base_time); |
| 373 | timestamp_add(TS_START_ROMSTAGE, start_romstage_time ); |
| 374 | timestamp_add(TS_BEFORE_INITRAM, before_dram_time ); |
| 375 | timestamp_add(TS_AFTER_INITRAM, after_dram_time ); |
| 376 | timestamp_add_now(TS_END_ROMSTAGE); |
| 377 | #endif |
| 378 | #if CONFIG_CONSOLE_CBMEM |
| 379 | /* Keep this the last thing this function does. */ |
| 380 | cbmemc_reinit(); |
| 381 | #endif |
| 382 | } |