Jianjun Wang | 270b0b6 | 2021-07-14 15:38:19 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
Jianjun Wang | 7439a49 | 2022-03-31 15:37:25 +0800 | [diff] [blame^] | 3 | #include <boot/coreboot_tables.h> |
Jianjun Wang | 270b0b6 | 2021-07-14 15:38:19 +0800 | [diff] [blame] | 4 | #include <commonlib/stdlib.h> |
| 5 | #include <console/console.h> |
| 6 | #include <device/device.h> |
| 7 | #include <device/mmio.h> |
| 8 | #include <device/pci.h> |
| 9 | #include <device/pci_def.h> |
| 10 | #include <device/pci_ids.h> |
| 11 | #include <device/resource.h> |
| 12 | #include <delay.h> |
| 13 | #include <lib.h> |
| 14 | #include <soc/addressmap.h> |
Jianjun Wang | aa751cc | 2022-03-23 15:38:56 +0800 | [diff] [blame] | 15 | #include <soc/early_init.h> |
Jianjun Wang | 270b0b6 | 2021-07-14 15:38:19 +0800 | [diff] [blame] | 16 | #include <soc/pcie.h> |
| 17 | #include <soc/pcie_common.h> |
Jianjun Wang | c0808b6 | 2022-03-14 20:38:18 +0800 | [diff] [blame] | 18 | #include <soc/soc_chip.h> |
Jianjun Wang | 270b0b6 | 2021-07-14 15:38:19 +0800 | [diff] [blame] | 19 | #include <stdlib.h> |
| 20 | #include <types.h> |
| 21 | |
| 22 | #define PCIE_SETTING_REG 0x80 |
| 23 | #define PCIE_PCI_IDS_1 0x9c |
| 24 | #define PCI_CLASS(class) ((class) << 8) |
| 25 | #define PCIE_RC_MODE BIT(0) |
| 26 | |
| 27 | #define PCIE_CFGNUM_REG 0x140 |
| 28 | #define PCIE_CFG_DEVFN(devfn) ((devfn) & GENMASK(7, 0)) |
| 29 | #define PCIE_CFG_BUS(bus) (((bus) << 8) & GENMASK(15, 8)) |
| 30 | #define PCIE_CFG_OFFSET_ADDR 0x1000 |
| 31 | #define PCIE_CFG_HEADER(bus, devfn) \ |
| 32 | (PCIE_CFG_BUS(bus) | PCIE_CFG_DEVFN(devfn)) |
| 33 | |
| 34 | #define PCIE_RST_CTRL_REG 0x148 |
| 35 | #define PCIE_MAC_RSTB BIT(0) |
| 36 | #define PCIE_PHY_RSTB BIT(1) |
| 37 | #define PCIE_BRG_RSTB BIT(2) |
| 38 | #define PCIE_PE_RSTB BIT(3) |
| 39 | |
| 40 | #define PCIE_LTSSM_STATUS_REG 0x150 |
| 41 | #define PCIE_LTSSM_STATE(val) (((val) >> 24) & 0x1f) |
| 42 | |
| 43 | #define PCIE_LINK_STATUS_REG 0x154 |
| 44 | #define PCIE_CTRL_LINKUP BIT(8) |
| 45 | |
| 46 | #define PCI_NUM_INTX 4 |
| 47 | #define PCIE_INT_ENABLE_REG 0x180 |
| 48 | #define PCIE_INTX_SHIFT 24 |
| 49 | #define PCIE_INTX_ENABLE \ |
| 50 | GENMASK(PCIE_INTX_SHIFT + PCI_NUM_INTX - 1, PCIE_INTX_SHIFT) |
| 51 | |
| 52 | #define PCIE_TRANS_TABLE_BASE_REG 0x800 |
| 53 | #define PCIE_ATR_SRC_ADDR_MSB_OFFSET 0x4 |
| 54 | #define PCIE_ATR_TRSL_ADDR_LSB_OFFSET 0x8 |
| 55 | #define PCIE_ATR_TRSL_ADDR_MSB_OFFSET 0xc |
| 56 | #define PCIE_ATR_TRSL_PARAM_OFFSET 0x10 |
| 57 | #define PCIE_ATR_TLB_SET_OFFSET 0x20 |
| 58 | |
| 59 | #define PCIE_MAX_TRANS_TABLES 8 |
| 60 | #define PCIE_ATR_EN BIT(0) |
| 61 | #define PCIE_ATR_SIZE(size) \ |
| 62 | (((((size) - 1) << 1) & GENMASK(6, 1)) | PCIE_ATR_EN) |
| 63 | #define PCIE_ATR_ID(id) ((id) & GENMASK(3, 0)) |
| 64 | #define PCIE_ATR_TYPE_MEM PCIE_ATR_ID(0) |
| 65 | #define PCIE_ATR_TYPE_IO PCIE_ATR_ID(1) |
| 66 | #define PCIE_ATR_TLP_TYPE(type) (((type) << 16) & GENMASK(18, 16)) |
| 67 | #define PCIE_ATR_TLP_TYPE_MEM PCIE_ATR_TLP_TYPE(0) |
| 68 | #define PCIE_ATR_TLP_TYPE_IO PCIE_ATR_TLP_TYPE(2) |
| 69 | |
Jianjun Wang | 270b0b6 | 2021-07-14 15:38:19 +0800 | [diff] [blame] | 70 | /* LTSSM state in PCIE_LTSSM_STATUS_REG bit[28:24] */ |
| 71 | static const char *const ltssm_str[] = { |
| 72 | "detect.quiet", /* 0x00 */ |
| 73 | "detect.active", /* 0x01 */ |
| 74 | "polling.active", /* 0x02 */ |
| 75 | "polling.compliance", /* 0x03 */ |
| 76 | "polling.configuration", /* 0x04 */ |
| 77 | "config.linkwidthstart", /* 0x05 */ |
| 78 | "config.linkwidthaccept", /* 0x06 */ |
| 79 | "config.lanenumwait", /* 0x07 */ |
| 80 | "config.lanenumaccept", /* 0x08 */ |
| 81 | "config.complete", /* 0x09 */ |
| 82 | "config.idle", /* 0x0A */ |
| 83 | "recovery.receiverlock", /* 0x0B */ |
| 84 | "recovery.equalization", /* 0x0C */ |
| 85 | "recovery.speed", /* 0x0D */ |
| 86 | "recovery.receiverconfig", /* 0x0E */ |
| 87 | "recovery.idle", /* 0x0F */ |
| 88 | "L0", /* 0x10 */ |
| 89 | "L0s", /* 0x11 */ |
| 90 | "L1.entry", /* 0x12 */ |
| 91 | "L1.idle", /* 0x13 */ |
| 92 | "L2.idle", /* 0x14 */ |
| 93 | "L2.transmitwake", /* 0x15 */ |
| 94 | "disable", /* 0x16 */ |
| 95 | "loopback.entry", /* 0x17 */ |
| 96 | "loopback.active", /* 0x18 */ |
| 97 | "loopback.exit", /* 0x19 */ |
| 98 | "hotreset", /* 0x1A */ |
| 99 | }; |
| 100 | |
Jianjun Wang | 5111326 | 2022-03-15 13:43:14 +0800 | [diff] [blame] | 101 | static uintptr_t mtk_pcie_get_controller_base(pci_devfn_t devfn) |
| 102 | { |
| 103 | struct device *root_dev; |
| 104 | const mtk_soc_config_t *config; |
| 105 | static uintptr_t base = 0; |
| 106 | |
| 107 | if (!base) { |
| 108 | root_dev = pcidev_path_on_root(devfn); |
| 109 | config = config_of(root_dev); |
| 110 | base = config->pcie_config.base; |
| 111 | } |
| 112 | |
| 113 | return base; |
| 114 | } |
| 115 | |
Jianjun Wang | 270b0b6 | 2021-07-14 15:38:19 +0800 | [diff] [blame] | 116 | volatile union pci_bank *pci_map_bus(pci_devfn_t dev) |
| 117 | { |
| 118 | u32 val, devfn, bus; |
Jianjun Wang | 5111326 | 2022-03-15 13:43:14 +0800 | [diff] [blame] | 119 | uintptr_t base; |
Jianjun Wang | 270b0b6 | 2021-07-14 15:38:19 +0800 | [diff] [blame] | 120 | |
| 121 | devfn = PCI_DEV2DEVFN(dev); |
| 122 | bus = PCI_DEV2SEGBUS(dev); |
| 123 | val = PCIE_CFG_HEADER(bus, devfn); |
| 124 | |
Jianjun Wang | 5111326 | 2022-03-15 13:43:14 +0800 | [diff] [blame] | 125 | base = mtk_pcie_get_controller_base(dev); |
| 126 | write32p(base + PCIE_CFGNUM_REG, val); |
Jianjun Wang | 270b0b6 | 2021-07-14 15:38:19 +0800 | [diff] [blame] | 127 | |
Jianjun Wang | 5111326 | 2022-03-15 13:43:14 +0800 | [diff] [blame] | 128 | return (void *)(base + PCIE_CFG_OFFSET_ADDR); |
Jianjun Wang | 270b0b6 | 2021-07-14 15:38:19 +0800 | [diff] [blame] | 129 | } |
| 130 | |
| 131 | static int mtk_pcie_set_trans_window(struct device *dev, uintptr_t table, |
| 132 | const struct mtk_pcie_mmio_res *mmio_res) |
| 133 | { |
| 134 | const char *range_type; |
| 135 | uint32_t table_attr; |
| 136 | |
| 137 | if (!mmio_res) |
| 138 | return -1; |
| 139 | |
| 140 | if (mmio_res->type == IORESOURCE_IO) { |
| 141 | range_type = "IO"; |
| 142 | table_attr = PCIE_ATR_TYPE_IO | PCIE_ATR_TLP_TYPE_IO; |
| 143 | } else if (mmio_res->type == IORESOURCE_MEM) { |
| 144 | range_type = "MEM"; |
| 145 | table_attr = PCIE_ATR_TYPE_MEM | PCIE_ATR_TLP_TYPE_MEM; |
| 146 | } else { |
| 147 | printk(BIOS_ERR, "%s: Unknown trans table type %#lx\n", |
| 148 | __func__, mmio_res->type); |
| 149 | return -1; |
| 150 | } |
| 151 | |
| 152 | write32p(table, mmio_res->cpu_addr | |
| 153 | PCIE_ATR_SIZE(__fls(mmio_res->size))); |
| 154 | write32p(table + PCIE_ATR_SRC_ADDR_MSB_OFFSET, 0); |
| 155 | write32p(table + PCIE_ATR_TRSL_ADDR_LSB_OFFSET, mmio_res->pci_addr); |
| 156 | write32p(table + PCIE_ATR_TRSL_ADDR_MSB_OFFSET, 0); |
| 157 | write32p(table + PCIE_ATR_TRSL_PARAM_OFFSET, table_attr); |
| 158 | |
| 159 | printk(BIOS_INFO, |
| 160 | "%s: set %s trans window: cpu_addr = %#x, pci_addr = %#x, size = %#x\n", |
| 161 | __func__, range_type, mmio_res->cpu_addr, mmio_res->pci_addr, |
| 162 | mmio_res->size); |
| 163 | |
| 164 | return 0; |
| 165 | } |
| 166 | |
| 167 | static void mtk_pcie_domain_new_res(struct device *dev, unsigned int index, |
| 168 | const struct mtk_pcie_mmio_res *mmio_res) |
| 169 | { |
| 170 | struct resource *res; |
| 171 | |
| 172 | if (!mmio_res) |
| 173 | return; |
| 174 | |
| 175 | res = new_resource(dev, index); |
| 176 | res->base = mmio_res->cpu_addr; |
| 177 | res->limit = mmio_res->cpu_addr + mmio_res->size - 1; |
| 178 | res->flags = mmio_res->type | IORESOURCE_SUBTRACTIVE | |
| 179 | IORESOURCE_ASSIGNED; |
| 180 | } |
| 181 | |
| 182 | void mtk_pcie_domain_read_resources(struct device *dev) |
| 183 | { |
Jianjun Wang | c0808b6 | 2022-03-14 20:38:18 +0800 | [diff] [blame] | 184 | const mtk_soc_config_t *config = config_of(dev); |
| 185 | const struct mtk_pcie_config *conf = &config->pcie_config; |
Jianjun Wang | 270b0b6 | 2021-07-14 15:38:19 +0800 | [diff] [blame] | 186 | |
| 187 | mtk_pcie_domain_new_res(dev, IOINDEX_SUBTRACTIVE(0, 0), |
Jianjun Wang | c0808b6 | 2022-03-14 20:38:18 +0800 | [diff] [blame] | 188 | &conf->mmio_res_io); |
Jianjun Wang | 270b0b6 | 2021-07-14 15:38:19 +0800 | [diff] [blame] | 189 | |
| 190 | mtk_pcie_domain_new_res(dev, IOINDEX_SUBTRACTIVE(1, 0), |
Jianjun Wang | c0808b6 | 2022-03-14 20:38:18 +0800 | [diff] [blame] | 191 | &conf->mmio_res_mem); |
Jianjun Wang | 270b0b6 | 2021-07-14 15:38:19 +0800 | [diff] [blame] | 192 | } |
| 193 | |
| 194 | void mtk_pcie_domain_set_resources(struct device *dev) |
| 195 | { |
Jianjun Wang | c0808b6 | 2022-03-14 20:38:18 +0800 | [diff] [blame] | 196 | const mtk_soc_config_t *config = config_of(dev); |
| 197 | const struct mtk_pcie_config *conf = &config->pcie_config; |
Jianjun Wang | 270b0b6 | 2021-07-14 15:38:19 +0800 | [diff] [blame] | 198 | uintptr_t table; |
| 199 | |
| 200 | /* Initialize I/O space constraints. */ |
Jianjun Wang | c0808b6 | 2022-03-14 20:38:18 +0800 | [diff] [blame] | 201 | table = conf->base + PCIE_TRANS_TABLE_BASE_REG; |
| 202 | if (mtk_pcie_set_trans_window(dev, table, &conf->mmio_res_io) < 0) |
Jianjun Wang | 270b0b6 | 2021-07-14 15:38:19 +0800 | [diff] [blame] | 203 | printk(BIOS_ERR, "%s: Failed to set IO window\n", __func__); |
| 204 | |
| 205 | /* Initialize memory resources constraints. */ |
Jianjun Wang | c0808b6 | 2022-03-14 20:38:18 +0800 | [diff] [blame] | 206 | table = conf->base + PCIE_TRANS_TABLE_BASE_REG + |
Jianjun Wang | 270b0b6 | 2021-07-14 15:38:19 +0800 | [diff] [blame] | 207 | PCIE_ATR_TLB_SET_OFFSET; |
Jianjun Wang | c0808b6 | 2022-03-14 20:38:18 +0800 | [diff] [blame] | 208 | if (mtk_pcie_set_trans_window(dev, table, &conf->mmio_res_mem) < 0) |
Jianjun Wang | 270b0b6 | 2021-07-14 15:38:19 +0800 | [diff] [blame] | 209 | printk(BIOS_ERR, "%s: Failed to set MEM window\n", __func__); |
| 210 | |
| 211 | pci_domain_set_resources(dev); |
| 212 | } |
| 213 | |
Jianjun Wang | 7439a49 | 2022-03-31 15:37:25 +0800 | [diff] [blame^] | 214 | enum cb_err lb_fill_pcie(struct lb_pcie *pcie) |
| 215 | { |
| 216 | if (!pci_root_bus()) |
| 217 | return CB_ERR; |
| 218 | |
| 219 | pcie->ctrl_base = mtk_pcie_get_controller_base(0); |
| 220 | return CB_SUCCESS; |
| 221 | } |
| 222 | |
Jianjun Wang | 270b0b6 | 2021-07-14 15:38:19 +0800 | [diff] [blame] | 223 | void mtk_pcie_domain_enable(struct device *dev) |
| 224 | { |
Jianjun Wang | c0808b6 | 2022-03-14 20:38:18 +0800 | [diff] [blame] | 225 | const mtk_soc_config_t *config = config_of(dev); |
Jianjun Wang | 5111326 | 2022-03-15 13:43:14 +0800 | [diff] [blame] | 226 | const struct mtk_pcie_config *conf = &config->pcie_config; |
Jianjun Wang | c0808b6 | 2022-03-14 20:38:18 +0800 | [diff] [blame] | 227 | const char *ltssm_state; |
Jianjun Wang | 79b35ca | 2022-03-30 09:09:43 +0800 | [diff] [blame] | 228 | long perst_time_us; |
Jianjun Wang | c0808b6 | 2022-03-14 20:38:18 +0800 | [diff] [blame] | 229 | size_t tries = 0; |
| 230 | uint32_t val; |
Jianjun Wang | 270b0b6 | 2021-07-14 15:38:19 +0800 | [diff] [blame] | 231 | |
Jianjun Wang | c0808b6 | 2022-03-14 20:38:18 +0800 | [diff] [blame] | 232 | /* Set as RC mode */ |
Jianjun Wang | 5111326 | 2022-03-15 13:43:14 +0800 | [diff] [blame] | 233 | val = read32p(conf->base + PCIE_SETTING_REG); |
Jianjun Wang | c0808b6 | 2022-03-14 20:38:18 +0800 | [diff] [blame] | 234 | val |= PCIE_RC_MODE; |
Jianjun Wang | 5111326 | 2022-03-15 13:43:14 +0800 | [diff] [blame] | 235 | write32p(conf->base + PCIE_SETTING_REG, val); |
Jianjun Wang | c0808b6 | 2022-03-14 20:38:18 +0800 | [diff] [blame] | 236 | |
| 237 | /* Set class code */ |
Jianjun Wang | 5111326 | 2022-03-15 13:43:14 +0800 | [diff] [blame] | 238 | val = read32p(conf->base + PCIE_PCI_IDS_1); |
Jianjun Wang | c0808b6 | 2022-03-14 20:38:18 +0800 | [diff] [blame] | 239 | val &= ~GENMASK(31, 8); |
| 240 | val |= PCI_CLASS(PCI_CLASS_BRIDGE_PCI << 8); |
Jianjun Wang | 5111326 | 2022-03-15 13:43:14 +0800 | [diff] [blame] | 241 | write32p(conf->base + PCIE_PCI_IDS_1, val); |
Jianjun Wang | c0808b6 | 2022-03-14 20:38:18 +0800 | [diff] [blame] | 242 | |
| 243 | /* Mask all INTx interrupts */ |
Jianjun Wang | 5111326 | 2022-03-15 13:43:14 +0800 | [diff] [blame] | 244 | val = read32p(conf->base + PCIE_INT_ENABLE_REG); |
Jianjun Wang | c0808b6 | 2022-03-14 20:38:18 +0800 | [diff] [blame] | 245 | val &= ~PCIE_INTX_ENABLE; |
Jianjun Wang | 5111326 | 2022-03-15 13:43:14 +0800 | [diff] [blame] | 246 | write32p(conf->base + PCIE_INT_ENABLE_REG, val); |
Jianjun Wang | c0808b6 | 2022-03-14 20:38:18 +0800 | [diff] [blame] | 247 | |
Jianjun Wang | aa751cc | 2022-03-23 15:38:56 +0800 | [diff] [blame] | 248 | perst_time_us = early_init_get_elapsed_time_us(EARLY_INIT_PCIE); |
Jianjun Wang | 79b35ca | 2022-03-30 09:09:43 +0800 | [diff] [blame] | 249 | printk(BIOS_DEBUG, "%s: %ld us elapsed since assert PERST#\n", |
Jianjun Wang | aa751cc | 2022-03-23 15:38:56 +0800 | [diff] [blame] | 250 | __func__, perst_time_us); |
| 251 | |
| 252 | /* |
| 253 | * Described in PCIe CEM specification sections 2.2 |
| 254 | * (PERST# Signal) and 2.2.1 (Initial Power-Up (G3 to S0)). |
| 255 | * The deassertion of PERST# should be delayed 100ms (TPVPERL) |
| 256 | * for the power and clock to become stable. |
| 257 | */ |
Jianjun Wang | 79b35ca | 2022-03-30 09:09:43 +0800 | [diff] [blame] | 258 | const long min_perst_time_us = 100000; /* 100 ms */ |
Jianjun Wang | aa751cc | 2022-03-23 15:38:56 +0800 | [diff] [blame] | 259 | if (perst_time_us < min_perst_time_us) { |
| 260 | if (!perst_time_us) { |
| 261 | printk(BIOS_WARNING, |
| 262 | "%s: PCIe early init data not found, sleeping 100ms\n", |
| 263 | __func__); |
| 264 | mtk_pcie_reset(conf->base + PCIE_RST_CTRL_REG, true); |
| 265 | } else { |
| 266 | printk(BIOS_WARNING, |
Jianjun Wang | 79b35ca | 2022-03-30 09:09:43 +0800 | [diff] [blame] | 267 | "%s: Need an extra %ld us delay to meet PERST# deassertion requirement\n", |
Jianjun Wang | aa751cc | 2022-03-23 15:38:56 +0800 | [diff] [blame] | 268 | __func__, min_perst_time_us - perst_time_us); |
| 269 | } |
| 270 | |
| 271 | udelay(min_perst_time_us - perst_time_us); |
| 272 | } |
| 273 | |
Jianjun Wang | c0808b6 | 2022-03-14 20:38:18 +0800 | [diff] [blame] | 274 | /* De-assert reset signals */ |
Jianjun Wang | 5111326 | 2022-03-15 13:43:14 +0800 | [diff] [blame] | 275 | mtk_pcie_reset(conf->base + PCIE_RST_CTRL_REG, false); |
Jianjun Wang | c0808b6 | 2022-03-14 20:38:18 +0800 | [diff] [blame] | 276 | |
| 277 | if (!retry(100, |
Jianjun Wang | 5111326 | 2022-03-15 13:43:14 +0800 | [diff] [blame] | 278 | (tries++, read32p(conf->base + PCIE_LINK_STATUS_REG) & |
Jianjun Wang | c0808b6 | 2022-03-14 20:38:18 +0800 | [diff] [blame] | 279 | PCIE_CTRL_LINKUP), mdelay(1))) { |
Jianjun Wang | 5111326 | 2022-03-15 13:43:14 +0800 | [diff] [blame] | 280 | val = read32p(conf->base + PCIE_LTSSM_STATUS_REG); |
Jianjun Wang | c0808b6 | 2022-03-14 20:38:18 +0800 | [diff] [blame] | 281 | ltssm_state = PCIE_LTSSM_STATE(val) >= ARRAY_SIZE(ltssm_str) ? |
| 282 | "Unknown state" : ltssm_str[PCIE_LTSSM_STATE(val)]; |
| 283 | printk(BIOS_ERR, "%s: PCIe link down, current ltssm state: %s\n", |
| 284 | __func__, ltssm_state); |
Jianjun Wang | 270b0b6 | 2021-07-14 15:38:19 +0800 | [diff] [blame] | 285 | return; |
Jianjun Wang | c0808b6 | 2022-03-14 20:38:18 +0800 | [diff] [blame] | 286 | } |
Jianjun Wang | 270b0b6 | 2021-07-14 15:38:19 +0800 | [diff] [blame] | 287 | |
Jianjun Wang | c0808b6 | 2022-03-14 20:38:18 +0800 | [diff] [blame] | 288 | printk(BIOS_INFO, "%s: PCIe link up success (%ld tries)\n", __func__, |
| 289 | tries); |
Jianjun Wang | 270b0b6 | 2021-07-14 15:38:19 +0800 | [diff] [blame] | 290 | } |