soc/mediatek: Fill coreboot table with PCIe info
In order to pass PCIe base address to payloads, implement pcie_fill_lb()
to fill coreboot table with PCIe info.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
BRANCH=cherry
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Ib2988694f60aac9cbfc09ef9a26d47e01c004406
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
diff --git a/src/soc/mediatek/common/pcie.c b/src/soc/mediatek/common/pcie.c
index bcae4b5..febb76d 100644
--- a/src/soc/mediatek/common/pcie.c
+++ b/src/soc/mediatek/common/pcie.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <boot/coreboot_tables.h>
#include <commonlib/stdlib.h>
#include <console/console.h>
#include <device/device.h>
@@ -210,6 +211,15 @@
pci_domain_set_resources(dev);
}
+enum cb_err lb_fill_pcie(struct lb_pcie *pcie)
+{
+ if (!pci_root_bus())
+ return CB_ERR;
+
+ pcie->ctrl_base = mtk_pcie_get_controller_base(0);
+ return CB_SUCCESS;
+}
+
void mtk_pcie_domain_enable(struct device *dev)
{
const mtk_soc_config_t *config = config_of(dev);