blob: 2c1d961debe800cda2ea55aa30f391d437c093a1 [file] [log] [blame]
Patrick Georgi23f38cd2012-11-16 14:50:32 +01001ramstage-y += model_206ax_init.c
Stefan Reinauer5c554632012-04-04 00:09:50 +02002subdirs-y += ../../x86/name
Vladimir Serbinenkoc16e9dfa2015-05-29 16:18:01 +02003subdirs-y += ../smm/gen1
Matt DeVilliered6fe2f2016-12-14 16:12:43 -06004subdirs-y += ../common
Stefan Reinauer5c554632012-04-04 00:09:50 +02005
Vladimir Serbinenko822bc652014-01-03 15:55:40 +01006ramstage-y += acpi.c
Stefan Reinauer5c554632012-04-04 00:09:50 +02007
Patrick Rudolph74203de2017-11-20 11:57:01 +01008ramstage-y += common.c
9romstage-y += common.c
10smm-$(CONFIG_HAVE_SMI_HANDLER) += common.c
11
Patrick Rudolphb9959e22017-06-06 10:44:29 +020012ramstage-y += tsc_freq.c
13romstage-y += tsc_freq.c
14smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
15
Stefan Reinauer5c554632012-04-04 00:09:50 +020016smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
17
Arthur Heymans67031a52018-02-05 19:08:03 +010018romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
Arthur Heymans6fcd7b82018-06-03 12:16:24 +020019postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
Arthur Heymans67031a52018-02-05 19:08:03 +010020ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
21
Alexandru Gagniuc1d857002015-09-09 22:38:06 -070022cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
23cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
Alexandru Gagniuc00b579a2012-07-20 00:11:21 -050024
Arthur Heymansdd4d8952018-06-03 12:04:26 +020025cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S
26postcar-y += ../car/non-evict/exit_car.S
Arthur Heymansdd4d8952018-06-03 12:04:26 +020027
Kyösti Mälkki75d139b2016-06-17 10:00:28 +030028romstage-y += ../car/romstage.c