| Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| Duncan Laurie | f6763db | 2013-03-22 11:01:37 -0700 | [diff] [blame] | 5 | * Copyright 2011 Google Inc. |
| Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| Duncan Laurie | f6763db | 2013-03-22 11:01:37 -0700 | [diff] [blame] | 21 | #define ENABLE_TPM |
| 22 | |
| Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 23 | DefinitionBlock( |
| 24 | "dsdt.aml", |
| 25 | "DSDT", |
| 26 | 0x02, // DSDT revision: ACPI v2.0 |
| 27 | "COREv4", // OEM id |
| Martin Roth | 73d5d4c | 2014-08-11 11:59:30 -0600 | [diff] [blame^] | 28 | "COREBOOT", // OEM table id |
| Aaron Durbin | f6933a6 | 2012-10-30 09:09:39 -0500 | [diff] [blame] | 29 | 0x20110725 // OEM revision |
| 30 | ) |
| 31 | { |
| 32 | // Some generic macros |
| 33 | #include "acpi/platform.asl" |
| 34 | |
| 35 | // global NVS and variables |
| 36 | #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> |
| 37 | |
| 38 | // General Purpose Events |
| 39 | //#include "acpi/gpe.asl" |
| 40 | |
| 41 | #include "acpi/thermal.asl" |
| 42 | |
| 43 | #include "../../../cpu/intel/haswell/acpi/cpu.asl" |
| 44 | |
| 45 | Scope (\_SB) { |
| 46 | Device (PCI0) |
| 47 | { |
| 48 | #include <northbridge/intel/haswell/acpi/haswell.asl> |
| 49 | #include <southbridge/intel/lynxpoint/acpi/pch.asl> |
| 50 | } |
| 51 | } |
| 52 | |
| 53 | #include "acpi/chromeos.asl" |
| 54 | #include <vendorcode/google/chromeos/acpi/chromeos.asl> |
| 55 | |
| 56 | /* Chipset specific sleep states */ |
| 57 | #include <southbridge/intel/lynxpoint/acpi/sleepstates.asl> |
| 58 | } |