blob: 79bb8f39f8554f87f1b597d0105ee3f088e17f08 [file] [log] [blame]
Aaron Durbinf6933a62012-10-30 09:09:39 -05001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2009 coresystems GmbH
5 * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21DefinitionBlock(
22 "dsdt.aml",
23 "DSDT",
24 0x02, // DSDT revision: ACPI v2.0
25 "COREv4", // OEM id
26 "COREBOOT", // OEM table id
27 0x20110725 // OEM revision
28)
29{
30 // Some generic macros
31 #include "acpi/platform.asl"
32
33 // global NVS and variables
34 #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
35
36 // General Purpose Events
37 //#include "acpi/gpe.asl"
38
39 #include "acpi/thermal.asl"
40
41 #include "../../../cpu/intel/haswell/acpi/cpu.asl"
42
43 Scope (\_SB) {
44 Device (PCI0)
45 {
46 #include <northbridge/intel/haswell/acpi/haswell.asl>
47 #include <southbridge/intel/lynxpoint/acpi/pch.asl>
48 }
49 }
50
51 #include "acpi/chromeos.asl"
52 #include <vendorcode/google/chromeos/acpi/chromeos.asl>
53
54 /* Chipset specific sleep states */
55 #include <southbridge/intel/lynxpoint/acpi/sleepstates.asl>
56}