Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Google Inc. |
Lee Leahy | a608969 | 2016-01-05 16:34:58 -0800 | [diff] [blame] | 5 | * Copyright (C) 2015-2016 Intel Corporation. |
Frans Hendriks | 44d2c85 | 2018-12-03 10:40:06 +0100 | [diff] [blame] | 6 | * Copyright (C) 2018 Eltan B.V. |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #include <stddef.h> |
Aaron Durbin | 932e09d | 2016-07-13 23:09:52 -0500 | [diff] [blame] | 19 | #include <arch/acpi.h> |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 20 | #include <arch/cbfs.h> |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 21 | #include <assert.h> |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 22 | #include <console/console.h> |
| 23 | #include <cbmem.h> |
Patrick Rudolph | f677d17 | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 24 | #include <cf9_reset.h> |
robbie zhang | 13a2e94 | 2016-02-10 11:40:11 -0800 | [diff] [blame] | 25 | #include <cpu/intel/microcode.h> |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 26 | #include <cpu/x86/mtrr.h> |
| 27 | #include <ec/google/chromeec/ec.h> |
| 28 | #include <ec/google/chromeec/ec_commands.h> |
| 29 | #include <elog.h> |
Lee Leahy | b092c9e | 2016-01-01 18:09:50 -0800 | [diff] [blame] | 30 | #include <fsp/romstage.h> |
Aaron Durbin | decd062 | 2017-12-15 12:26:40 -0700 | [diff] [blame] | 31 | #include <mrc_cache.h> |
Kyösti Mälkki | 65e8f64 | 2016-06-27 11:27:56 +0300 | [diff] [blame] | 32 | #include <program_loading.h> |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 33 | #include <romstage_handoff.h> |
Lee Leahy | 0be6d93 | 2015-06-26 11:15:42 -0700 | [diff] [blame] | 34 | #include <smbios.h> |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 35 | #include <stage_cache.h> |
Aaron Durbin | afe8aee | 2016-11-29 21:37:42 -0600 | [diff] [blame] | 36 | #include <string.h> |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 37 | #include <timestamp.h> |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 38 | #include <vendorcode/google/chromeos/chromeos.h> |
| 39 | |
Arthur Heymans | be291e8 | 2019-01-06 07:35:11 +0100 | [diff] [blame] | 40 | asmlinkage void romstage_main(FSP_INFO_HEADER *fih) |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 41 | { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 42 | struct romstage_params params = { |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 43 | .chipset_context = fih, |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 44 | }; |
| 45 | |
| 46 | post_code(0x30); |
| 47 | |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 48 | timestamp_add_now(TS_START_ROMSTAGE); |
| 49 | |
Elyes HAOUAS | 7753731 | 2016-07-30 15:37:26 +0200 | [diff] [blame] | 50 | /* Load microcode before RAM init */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 51 | if (CONFIG(SUPPORT_CPU_UCODE_IN_CBFS)) |
robbie zhang | 13a2e94 | 2016-02-10 11:40:11 -0800 | [diff] [blame] | 52 | intel_update_microcode_from_cbfs(); |
| 53 | |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 54 | /* Display parameters */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 55 | if (!CONFIG(NO_MMCONF_SUPPORT)) |
Lee Leahy | c253a92 | 2017-03-13 17:36:39 -0700 | [diff] [blame] | 56 | printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n", |
| 57 | CONFIG_MMCONF_BASE_ADDRESS); |
Aaron Durbin | 929b602 | 2015-12-09 16:00:18 -0600 | [diff] [blame] | 58 | printk(BIOS_INFO, "Using FSP 1.1\n"); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 59 | |
| 60 | /* Display FSP banner */ |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 61 | print_fsp_info(fih); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 62 | |
Aaron Durbin | 929b602 | 2015-12-09 16:00:18 -0600 | [diff] [blame] | 63 | /* Stash FSP version. */ |
| 64 | params.fsp_version = fsp_version(fih); |
| 65 | |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 66 | /* Get power state */ |
| 67 | params.power_state = fill_power_state(); |
| 68 | |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 69 | /* Call into mainboard. */ |
| 70 | mainboard_romstage_entry(¶ms); |
| 71 | soc_after_ram_init(¶ms); |
| 72 | post_code(0x38); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 73 | } |
| 74 | |
Arthur Heymans | be291e8 | 2019-01-06 07:35:11 +0100 | [diff] [blame] | 75 | void cache_as_ram_stage_main(FSP_INFO_HEADER *fih) |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 76 | { |
Arthur Heymans | be291e8 | 2019-01-06 07:35:11 +0100 | [diff] [blame] | 77 | romstage_main(fih); |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 78 | } |
| 79 | |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 80 | /* Entry from the mainboard. */ |
| 81 | void romstage_common(struct romstage_params *params) |
| 82 | { |
Subrata Banik | 0beac81 | 2017-07-12 15:13:53 +0530 | [diff] [blame] | 83 | bool s3wake; |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 84 | struct region_device rdev; |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 85 | |
| 86 | post_code(0x32); |
| 87 | |
| 88 | timestamp_add_now(TS_BEFORE_INITRAM); |
| 89 | |
Subrata Banik | 0beac81 | 2017-07-12 15:13:53 +0530 | [diff] [blame] | 90 | s3wake = params->power_state->prev_sleep_state == ACPI_S3; |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 91 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 92 | if (CONFIG(ELOG_BOOT_COUNT) && !s3wake) |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 93 | boot_count_increment(); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 94 | |
| 95 | /* Perform remaining SOC initialization */ |
| 96 | soc_pre_ram_init(params); |
| 97 | post_code(0x33); |
| 98 | |
| 99 | /* Check recovery and MRC cache */ |
Nico Huber | 66318aa | 2019-05-04 16:59:20 +0200 | [diff] [blame] | 100 | params->saved_data_size = 0; |
| 101 | params->saved_data = NULL; |
| 102 | if (!params->disable_saved_data) { |
Furquan Shaikh | 0325dc6 | 2016-07-25 13:02:36 -0700 | [diff] [blame] | 103 | if (vboot_recovery_mode_enabled()) { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 104 | /* Recovery mode does not use MRC cache */ |
| 105 | printk(BIOS_DEBUG, |
| 106 | "Recovery mode: not using MRC cache.\n"); |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 107 | } else if (CONFIG(CACHE_MRC_SETTINGS) |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 108 | && (!mrc_cache_get_current(MRC_TRAINING_DATA, |
| 109 | params->fsp_version, |
| 110 | &rdev))) { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 111 | /* MRC cache found */ |
Nico Huber | 66318aa | 2019-05-04 16:59:20 +0200 | [diff] [blame] | 112 | params->saved_data_size = region_device_sz(&rdev); |
| 113 | params->saved_data = rdev_mmap_full(&rdev); |
Elyes HAOUAS | 1895838 | 2018-08-07 12:23:16 +0200 | [diff] [blame] | 114 | /* Assume boot device is memory mapped. */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 115 | assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); |
Nico Huber | 16895c5 | 2019-05-04 16:29:17 +0200 | [diff] [blame] | 116 | } else if (s3wake) { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 117 | /* Waking from S3 and no cache. */ |
| 118 | printk(BIOS_DEBUG, |
| 119 | "No MRC cache found in S3 resume path.\n"); |
| 120 | post_code(POST_RESUME_FAILURE); |
Patrick Rudolph | f677d17 | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 121 | /* FIXME: A "system" reset is likely enough: */ |
| 122 | full_reset(); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 123 | } else { |
| 124 | printk(BIOS_DEBUG, "No MRC cache found.\n"); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 125 | } |
| 126 | } |
| 127 | |
| 128 | /* Initialize RAM */ |
| 129 | raminit(params); |
| 130 | timestamp_add_now(TS_AFTER_INITRAM); |
| 131 | |
| 132 | /* Save MRC output */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 133 | if (CONFIG(CACHE_MRC_SETTINGS)) { |
Nico Huber | 66318aa | 2019-05-04 16:59:20 +0200 | [diff] [blame] | 134 | printk(BIOS_DEBUG, "MRC data at %p %zu bytes\n", |
| 135 | params->data_to_save, params->data_to_save_size); |
Nico Huber | 16895c5 | 2019-05-04 16:29:17 +0200 | [diff] [blame] | 136 | if (!s3wake |
Nico Huber | 66318aa | 2019-05-04 16:59:20 +0200 | [diff] [blame] | 137 | && (params->data_to_save_size != 0) |
| 138 | && (params->data_to_save != NULL)) |
Lee Leahy | 216712a | 2017-03-17 11:23:32 -0700 | [diff] [blame] | 139 | mrc_cache_stash_data(MRC_TRAINING_DATA, |
| 140 | params->fsp_version, |
Nico Huber | 66318aa | 2019-05-04 16:59:20 +0200 | [diff] [blame] | 141 | params->data_to_save, |
| 142 | params->data_to_save_size); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 143 | } |
| 144 | |
| 145 | /* Save DIMM information */ |
Subrata Banik | 0beac81 | 2017-07-12 15:13:53 +0530 | [diff] [blame] | 146 | if (!s3wake) |
| 147 | mainboard_save_dimm_info(params); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 148 | |
| 149 | /* Create romstage handof information */ |
Aaron Durbin | 77e1399 | 2016-11-29 17:43:04 -0600 | [diff] [blame] | 150 | if (romstage_handoff_init( |
| 151 | params->power_state->prev_sleep_state == ACPI_S3) < 0) |
Patrick Rudolph | f677d17 | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 152 | /* FIXME: A "system" reset is likely enough: */ |
| 153 | full_reset(); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 154 | } |
| 155 | |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 156 | /* Initialize the power state */ |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 157 | __weak struct chipset_power_state *fill_power_state(void) |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 158 | { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 159 | return NULL; |
| 160 | } |
| 161 | |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 162 | /* Board initialization before and after RAM is enabled */ |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 163 | __weak void mainboard_romstage_entry( |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 164 | struct romstage_params *params) |
| 165 | { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 166 | post_code(0x31); |
| 167 | |
Frans Hendriks | 44d2c85 | 2018-12-03 10:40:06 +0100 | [diff] [blame] | 168 | /* Initialize memory */ |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 169 | romstage_common(params); |
| 170 | } |
| 171 | |
| 172 | /* Save the DIMM information for SMBIOS table 17 */ |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 173 | __weak void mainboard_save_dimm_info( |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 174 | struct romstage_params *params) |
| 175 | { |
| 176 | int channel; |
| 177 | CHANNEL_INFO *channel_info; |
| 178 | int dimm; |
| 179 | DIMM_INFO *dimm_info; |
| 180 | int dimm_max; |
| 181 | void *hob_list_ptr; |
| 182 | EFI_HOB_GUID_TYPE *hob_ptr; |
| 183 | int index; |
| 184 | struct memory_info *mem_info; |
| 185 | FSP_SMBIOS_MEMORY_INFO *memory_info_hob; |
| 186 | const EFI_GUID memory_info_hob_guid = FSP_SMBIOS_MEMORY_INFO_GUID; |
| 187 | |
| 188 | /* Locate the memory info HOB, presence validated by raminit */ |
| 189 | hob_list_ptr = fsp_get_hob_list(); |
| 190 | hob_ptr = get_next_guid_hob(&memory_info_hob_guid, hob_list_ptr); |
| 191 | memory_info_hob = (FSP_SMBIOS_MEMORY_INFO *)(hob_ptr + 1); |
| 192 | |
| 193 | /* Display the data in the FSP_SMBIOS_MEMORY_INFO HOB */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 194 | if (CONFIG(DISPLAY_HOBS)) { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 195 | printk(BIOS_DEBUG, "FSP_SMBIOS_MEMORY_INFO HOB\n"); |
| 196 | printk(BIOS_DEBUG, " 0x%02x: Revision\n", |
| 197 | memory_info_hob->Revision); |
| 198 | printk(BIOS_DEBUG, " 0x%02x: MemoryType\n", |
| 199 | memory_info_hob->MemoryType); |
Lee Leahy | 0be6d93 | 2015-06-26 11:15:42 -0700 | [diff] [blame] | 200 | printk(BIOS_DEBUG, " %d: MemoryFrequencyInMHz\n", |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 201 | memory_info_hob->MemoryFrequencyInMHz); |
Lee Leahy | 0be6d93 | 2015-06-26 11:15:42 -0700 | [diff] [blame] | 202 | printk(BIOS_DEBUG, " %d: DataWidth in bits\n", |
| 203 | memory_info_hob->DataWidth); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 204 | printk(BIOS_DEBUG, " 0x%02x: ErrorCorrectionType\n", |
| 205 | memory_info_hob->ErrorCorrectionType); |
| 206 | printk(BIOS_DEBUG, " 0x%02x: ChannelCount\n", |
| 207 | memory_info_hob->ChannelCount); |
| 208 | for (channel = 0; channel < memory_info_hob->ChannelCount; |
| 209 | channel++) { |
| 210 | channel_info = &memory_info_hob->ChannelInfo[channel]; |
| 211 | printk(BIOS_DEBUG, " Channel %d\n", channel); |
| 212 | printk(BIOS_DEBUG, " 0x%02x: ChannelId\n", |
| 213 | channel_info->ChannelId); |
| 214 | printk(BIOS_DEBUG, " 0x%02x: DimmCount\n", |
| 215 | channel_info->DimmCount); |
| 216 | for (dimm = 0; dimm < channel_info->DimmCount; |
| 217 | dimm++) { |
| 218 | dimm_info = &channel_info->DimmInfo[dimm]; |
| 219 | printk(BIOS_DEBUG, " DIMM %d\n", dimm); |
| 220 | printk(BIOS_DEBUG, " 0x%02x: DimmId\n", |
| 221 | dimm_info->DimmId); |
Lee Leahy | 0be6d93 | 2015-06-26 11:15:42 -0700 | [diff] [blame] | 222 | printk(BIOS_DEBUG, " %d: SizeInMb\n", |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 223 | dimm_info->SizeInMb); |
| 224 | } |
| 225 | } |
| 226 | } |
| 227 | |
| 228 | /* |
| 229 | * Allocate CBMEM area for DIMM information used to populate SMBIOS |
| 230 | * table 17 |
| 231 | */ |
| 232 | mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); |
| 233 | printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", mem_info); |
| 234 | if (mem_info == NULL) |
| 235 | return; |
| 236 | memset(mem_info, 0, sizeof(*mem_info)); |
| 237 | |
| 238 | /* Describe the first N DIMMs in the system */ |
| 239 | index = 0; |
| 240 | dimm_max = ARRAY_SIZE(mem_info->dimm); |
| 241 | for (channel = 0; channel < memory_info_hob->ChannelCount; channel++) { |
| 242 | if (index >= dimm_max) |
| 243 | break; |
| 244 | channel_info = &memory_info_hob->ChannelInfo[channel]; |
| 245 | for (dimm = 0; dimm < channel_info->DimmCount; dimm++) { |
| 246 | if (index >= dimm_max) |
| 247 | break; |
| 248 | dimm_info = &channel_info->DimmInfo[dimm]; |
| 249 | |
| 250 | /* Populate the DIMM information */ |
| 251 | if (dimm_info->SizeInMb) { |
| 252 | mem_info->dimm[index].dimm_size = |
| 253 | dimm_info->SizeInMb; |
| 254 | mem_info->dimm[index].ddr_type = |
| 255 | memory_info_hob->MemoryType; |
| 256 | mem_info->dimm[index].ddr_frequency = |
| 257 | memory_info_hob->MemoryFrequencyInMHz; |
| 258 | mem_info->dimm[index].channel_num = |
| 259 | channel_info->ChannelId; |
| 260 | mem_info->dimm[index].dimm_num = |
| 261 | dimm_info->DimmId; |
Lee Leahy | 0be6d93 | 2015-06-26 11:15:42 -0700 | [diff] [blame] | 262 | switch (memory_info_hob->DataWidth) { |
| 263 | default: |
| 264 | case 8: |
| 265 | mem_info->dimm[index].bus_width = |
| 266 | MEMORY_BUS_WIDTH_8; |
| 267 | break; |
| 268 | |
| 269 | case 16: |
| 270 | mem_info->dimm[index].bus_width = |
| 271 | MEMORY_BUS_WIDTH_16; |
| 272 | break; |
| 273 | |
| 274 | case 32: |
| 275 | mem_info->dimm[index].bus_width = |
| 276 | MEMORY_BUS_WIDTH_32; |
| 277 | break; |
| 278 | |
| 279 | case 64: |
| 280 | mem_info->dimm[index].bus_width = |
| 281 | MEMORY_BUS_WIDTH_64; |
| 282 | break; |
| 283 | |
| 284 | case 128: |
| 285 | mem_info->dimm[index].bus_width = |
| 286 | MEMORY_BUS_WIDTH_128; |
| 287 | break; |
| 288 | } |
Duncan Laurie | 46a2c77 | 2015-07-20 16:48:55 -0700 | [diff] [blame] | 289 | |
| 290 | /* Add any mainboard specific information */ |
| 291 | mainboard_add_dimm_info(params, mem_info, |
| 292 | channel, dimm, index); |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 293 | index++; |
| 294 | } |
| 295 | } |
| 296 | } |
| 297 | mem_info->dimm_cnt = index; |
| 298 | printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); |
| 299 | } |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 300 | |
Duncan Laurie | 46a2c77 | 2015-07-20 16:48:55 -0700 | [diff] [blame] | 301 | /* Add any mainboard specific information */ |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 302 | __weak void mainboard_add_dimm_info( |
Duncan Laurie | 46a2c77 | 2015-07-20 16:48:55 -0700 | [diff] [blame] | 303 | struct romstage_params *params, |
| 304 | struct memory_info *mem_info, |
| 305 | int channel, int dimm, int index) |
| 306 | { |
Duncan Laurie | 46a2c77 | 2015-07-20 16:48:55 -0700 | [diff] [blame] | 307 | } |
| 308 | |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 309 | /* Get the memory configuration data */ |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 310 | __weak int mrc_cache_get_current(int type, uint32_t version, |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 311 | struct region_device *rdev) |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 312 | { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 313 | return -1; |
| 314 | } |
| 315 | |
| 316 | /* Save the memory configuration data */ |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 317 | __weak int mrc_cache_stash_data(int type, uint32_t version, |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 318 | const void *data, size_t size) |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 319 | { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 320 | return -1; |
| 321 | } |
| 322 | |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 323 | /* Display the memory configuration */ |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 324 | __weak void report_memory_config(void) |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 325 | { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 326 | } |
| 327 | |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 328 | /* SOC initialization after RAM is enabled */ |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 329 | __weak void soc_after_ram_init(struct romstage_params *params) |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 330 | { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 331 | } |
| 332 | |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 333 | /* SOC initialization before RAM is enabled */ |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 334 | __weak void soc_pre_ram_init(struct romstage_params *params) |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 335 | { |
Lee Leahy | 0946ec3 | 2015-04-20 15:24:54 -0700 | [diff] [blame] | 336 | } |