Blame - src/cpu/samsung/exynos5420/Kconfig - coreboot

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Stefan Reinauer	3511b92	2013-06-19 12:02:47 -0700	[diff] [blame]	1	config CPU_SAMSUNG_EXYNOS5420
				2	depends on ARCH_ARMV7
				3	select HAVE_MONOTONIC_TIMER
				4	select HAVE_UART_SPECIAL
Stefan Reinauer	d2f45c6	2013-06-19 13:42:00 -0700	[diff] [blame]	5	select EARLY_CONSOLE
Stefan Reinauer	80e6293	2013-07-29 15:52:23 -0700	[diff] [blame]	6	select DYNAMIC_CBMEM
Stefan Reinauer	3511b92	2013-06-19 12:02:47 -0700	[diff] [blame]	7	bool
				8	default n
				9
				10	if CPU_SAMSUNG_EXYNOS5420
				11
Gabe Black	607c0b6	2013-05-16 05:45:57 -0700	[diff] [blame]	12	config BOOTBLOCK_CPU_INIT
				13	string
				14	default "cpu/samsung/exynos5420/bootblock.c"
				15	help
				16	CPU/SoC-specific bootblock code. This is useful if the
				17	bootblock must load microcode or copy data from ROM before
				18	searching for the bootblock.
				19
Hung-Te Lin	d63bddc	2013-06-11 21:55:58 -0700	[diff] [blame]	20	# ROM image layout.
				21	#
				22	# 0x0000: vendor-provided BL1 (8k).
				23	# 0x2000: variable length bootblock checksum header
				24	# 0x2010: bootblock
				25	# 0x2020-0x20A0: reserved for CBFS master header.
				26	# 0xA000: Free for CBFS data.
				27
				28	config BOOTBLOCK_ROM_OFFSET
				29	hex
				30	default 0x2010
				31
				32	config CBFS_HEADER_ROM_OFFSET
				33	hex "offset of master CBFS header in ROM"
				34	default 0x2020
				35
				36	config CBFS_ROM_OFFSET
				37	# Calculated by BOOTBLOCK_ROM_OFFSET + max bootblock size.
				38	hex "offset of CBFS data in ROM"
				39	default 0x0A000
				40
Gabe Black	607c0b6	2013-05-16 05:45:57 -0700	[diff] [blame]	41
				42	# Example SRAM/iRAM map for Exynos5420 platform:
				43	#
				44	# 0x0202_0000: vendor-provided BL1
Hung-Te Lin	d63bddc	2013-06-11 21:55:58 -0700	[diff] [blame]	45	# 0x0202_4400: variable length bootblock checksum header.
				46	# 0x0202_4410: bootblock, assume up to 32KB in size
Gabe Black	607c0b6	2013-05-16 05:45:57 -0700	[diff] [blame]	47	# 0x0203_0000: romstage, assume up to 128KB in size.
Gabe Black	b2d811a	2013-05-13 15:56:53 -0700	[diff] [blame]	48	# 0x0207_4000: stack pointer
Gabe Black	607c0b6	2013-05-16 05:45:57 -0700	[diff] [blame]	49
				50	config BOOTBLOCK_BASE
				51	hex
Hung-Te Lin	d63bddc	2013-06-11 21:55:58 -0700	[diff] [blame]	52	default 0x02024410
Gabe Black	607c0b6	2013-05-16 05:45:57 -0700	[diff] [blame]	53
				54	config ROMSTAGE_BASE
				55	hex
				56	default 0x02030000
				57
				58	config ROMSTAGE_SIZE
				59	hex
				60	default 0x10000
				61
				62	# Stack may reside in either IRAM or DRAM. We will define it to live
				63	# at the top of IRAM for now.
				64	#
				65	# Stack grows downward, push operation stores register contents in
				66	# consecutive memory locations ending just below SP
				67	config STACK_TOP
				68	hex
Gabe Black	b2d811a	2013-05-13 15:56:53 -0700	[diff] [blame]	69	default 0x02074000
Gabe Black	607c0b6	2013-05-16 05:45:57 -0700	[diff] [blame]	70
				71	config STACK_BOTTOM
				72	hex
Gabe Black	b2d811a	2013-05-13 15:56:53 -0700	[diff] [blame]	73	default 0x02073000
Gabe Black	607c0b6	2013-05-16 05:45:57 -0700	[diff] [blame]	74
				75	config STACK_SIZE
				76	hex
				77	default 0x1000
				78
Gabe Black	607c0b6	2013-05-16 05:45:57 -0700	[diff] [blame]	79	# TODO We may probably move this to board-specific implementation files instead
				80	# of KConfig values.
				81	config CBFS_CACHE_ADDRESS
				82	hex "memory address to put CBFS cache data"
				83	default 0x02060000
				84
				85	config CBFS_CACHE_SIZE
				86	hex "size of CBFS cache data"
Gabe Black	b2d811a	2013-05-13 15:56:53 -0700	[diff] [blame]	87	default 0x000013000
Gabe Black	607c0b6	2013-05-16 05:45:57 -0700	[diff] [blame]	88
Gabe Black	607c0b6	2013-05-16 05:45:57 -0700	[diff] [blame]	89	config SYS_SDRAM_BASE
				90	hex
Gabe Black	b2d811a	2013-05-13 15:56:53 -0700	[diff] [blame]	91	default 0x20000000
Gabe Black	607c0b6	2013-05-16 05:45:57 -0700	[diff] [blame]	92
Gabe Black	607c0b6	2013-05-16 05:45:57 -0700	[diff] [blame]	93	choice CONSOLE_SERIAL_UART_CHOICES
				94	prompt "Serial Console UART"
				95	default CONSOLE_SERIAL_UART3
				96	depends on CONSOLE_SERIAL_UART
				97
				98	config CONSOLE_SERIAL_UART0
				99	bool "UART0"
				100	help
				101	Serial console on UART0
				102
				103	config CONSOLE_SERIAL_UART1
				104	bool "UART1"
				105	help
				106	Serial console on UART1
				107
				108	config CONSOLE_SERIAL_UART2
				109	bool "UART2"
				110	help
				111	Serial console on UART2
				112
				113	config CONSOLE_SERIAL_UART3
				114	bool "UART3"
				115	help
				116	Serial console on UART3
				117
				118	endchoice
				119
				120	config CONSOLE_SERIAL_UART_ADDRESS
				121	hex
				122	depends on CONSOLE_SERIAL_UART
				123	default 0x12c00000 if CONSOLE_SERIAL_UART0
				124	default 0x12c10000 if CONSOLE_SERIAL_UART1
				125	default 0x12c20000 if CONSOLE_SERIAL_UART2
				126	default 0x12c30000 if CONSOLE_SERIAL_UART3
				127	help
				128	Map the UART names to the respective MMIO address.
				129
Stefan Reinauer	3511b92	2013-06-19 12:02:47 -0700	[diff] [blame]	130	endif