Blame - src/cpu/samsung/exynos5420/Kconfig - coreboot

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Stefan Reinauer	3511b92	2013-06-19 12:02:47 -0700	[diff] [blame]	1	config CPU_SAMSUNG_EXYNOS5420
				2	depends on ARCH_ARMV7
				3	select HAVE_MONOTONIC_TIMER
				4	select HAVE_UART_SPECIAL
Stefan Reinauer	d2f45c6	2013-06-19 13:42:00 -0700	[diff] [blame^]	5	select EARLY_CONSOLE
Stefan Reinauer	3511b92	2013-06-19 12:02:47 -0700	[diff] [blame]	6	bool
				7	default n
				8
				9	if CPU_SAMSUNG_EXYNOS5420
				10
Gabe Black	607c0b6	2013-05-16 05:45:57 -0700	[diff] [blame]	11	config BOOTBLOCK_CPU_INIT
				12	string
				13	default "cpu/samsung/exynos5420/bootblock.c"
				14	help
				15	CPU/SoC-specific bootblock code. This is useful if the
				16	bootblock must load microcode or copy data from ROM before
				17	searching for the bootblock.
				18
Hung-Te Lin	d63bddc	2013-06-11 21:55:58 -0700	[diff] [blame]	19	# ROM image layout.
				20	#
				21	# 0x0000: vendor-provided BL1 (8k).
				22	# 0x2000: variable length bootblock checksum header
				23	# 0x2010: bootblock
				24	# 0x2020-0x20A0: reserved for CBFS master header.
				25	# 0xA000: Free for CBFS data.
				26
				27	config BOOTBLOCK_ROM_OFFSET
				28	hex
				29	default 0x2010
				30
				31	config CBFS_HEADER_ROM_OFFSET
				32	hex "offset of master CBFS header in ROM"
				33	default 0x2020
				34
				35	config CBFS_ROM_OFFSET
				36	# Calculated by BOOTBLOCK_ROM_OFFSET + max bootblock size.
				37	hex "offset of CBFS data in ROM"
				38	default 0x0A000
				39
Gabe Black	607c0b6	2013-05-16 05:45:57 -0700	[diff] [blame]	40
				41	# Example SRAM/iRAM map for Exynos5420 platform:
				42	#
				43	# 0x0202_0000: vendor-provided BL1
Hung-Te Lin	d63bddc	2013-06-11 21:55:58 -0700	[diff] [blame]	44	# 0x0202_4400: variable length bootblock checksum header.
				45	# 0x0202_4410: bootblock, assume up to 32KB in size
Gabe Black	607c0b6	2013-05-16 05:45:57 -0700	[diff] [blame]	46	# 0x0203_0000: romstage, assume up to 128KB in size.
Gabe Black	b2d811a	2013-05-13 15:56:53 -0700	[diff] [blame]	47	# 0x0207_4000: stack pointer
Gabe Black	607c0b6	2013-05-16 05:45:57 -0700	[diff] [blame]	48
				49	config BOOTBLOCK_BASE
				50	hex
Hung-Te Lin	d63bddc	2013-06-11 21:55:58 -0700	[diff] [blame]	51	default 0x02024410
Gabe Black	607c0b6	2013-05-16 05:45:57 -0700	[diff] [blame]	52
				53	config ROMSTAGE_BASE
				54	hex
				55	default 0x02030000
				56
				57	config ROMSTAGE_SIZE
				58	hex
				59	default 0x10000
				60
				61	# Stack may reside in either IRAM or DRAM. We will define it to live
				62	# at the top of IRAM for now.
				63	#
				64	# Stack grows downward, push operation stores register contents in
				65	# consecutive memory locations ending just below SP
				66	config STACK_TOP
				67	hex
Gabe Black	b2d811a	2013-05-13 15:56:53 -0700	[diff] [blame]	68	default 0x02074000
Gabe Black	607c0b6	2013-05-16 05:45:57 -0700	[diff] [blame]	69
				70	config STACK_BOTTOM
				71	hex
Gabe Black	b2d811a	2013-05-13 15:56:53 -0700	[diff] [blame]	72	default 0x02073000
Gabe Black	607c0b6	2013-05-16 05:45:57 -0700	[diff] [blame]	73
				74	config STACK_SIZE
				75	hex
				76	default 0x1000
				77
Gabe Black	607c0b6	2013-05-16 05:45:57 -0700	[diff] [blame]	78	# TODO We may probably move this to board-specific implementation files instead
				79	# of KConfig values.
				80	config CBFS_CACHE_ADDRESS
				81	hex "memory address to put CBFS cache data"
				82	default 0x02060000
				83
				84	config CBFS_CACHE_SIZE
				85	hex "size of CBFS cache data"
Gabe Black	b2d811a	2013-05-13 15:56:53 -0700	[diff] [blame]	86	default 0x000013000
Gabe Black	607c0b6	2013-05-16 05:45:57 -0700	[diff] [blame]	87
Gabe Black	607c0b6	2013-05-16 05:45:57 -0700	[diff] [blame]	88	config SYS_SDRAM_BASE
				89	hex
Gabe Black	b2d811a	2013-05-13 15:56:53 -0700	[diff] [blame]	90	default 0x20000000
Gabe Black	607c0b6	2013-05-16 05:45:57 -0700	[diff] [blame]	91
				92	config SYS_TEXT_BASE
				93	hex
Gabe Black	b2d811a	2013-05-13 15:56:53 -0700	[diff] [blame]	94	default 0x23e00000
Gabe Black	607c0b6	2013-05-16 05:45:57 -0700	[diff] [blame]	95
				96	config COREBOOT_TABLES_SIZE
				97	hex
				98	default 0x4000000
				99
				100	choice CONSOLE_SERIAL_UART_CHOICES
				101	prompt "Serial Console UART"
				102	default CONSOLE_SERIAL_UART3
				103	depends on CONSOLE_SERIAL_UART
				104
				105	config CONSOLE_SERIAL_UART0
				106	bool "UART0"
				107	help
				108	Serial console on UART0
				109
				110	config CONSOLE_SERIAL_UART1
				111	bool "UART1"
				112	help
				113	Serial console on UART1
				114
				115	config CONSOLE_SERIAL_UART2
				116	bool "UART2"
				117	help
				118	Serial console on UART2
				119
				120	config CONSOLE_SERIAL_UART3
				121	bool "UART3"
				122	help
				123	Serial console on UART3
				124
				125	endchoice
				126
				127	config CONSOLE_SERIAL_UART_ADDRESS
				128	hex
				129	depends on CONSOLE_SERIAL_UART
				130	default 0x12c00000 if CONSOLE_SERIAL_UART0
				131	default 0x12c10000 if CONSOLE_SERIAL_UART1
				132	default 0x12c20000 if CONSOLE_SERIAL_UART2
				133	default 0x12c30000 if CONSOLE_SERIAL_UART3
				134	help
				135	Map the UART names to the respective MMIO address.
				136
Stefan Reinauer	3511b92	2013-06-19 12:02:47 -0700	[diff] [blame]	137	endif