Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008-2009 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <console/console.h> |
Kyösti Mälkki | ab56b3b | 2013-11-28 16:44:51 +0200 | [diff] [blame] | 17 | #include <bootmode.h> |
Patrick Georgi | 6444bd4 | 2012-07-06 11:31:39 +0200 | [diff] [blame] | 18 | #include <delay.h> |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 19 | #include <device/device.h> |
| 20 | #include <device/pci.h> |
| 21 | #include <device/pci_ids.h> |
Sven Schnelle | b629d14 | 2011-06-12 14:30:10 +0200 | [diff] [blame] | 22 | #include <pc80/mc146818rtc.h> |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 23 | #include <edid.h> |
| 24 | #include <drivers/intel/gma/edid.h> |
| 25 | #include <drivers/intel/gma/i915.h> |
| 26 | #include <string.h> |
Vladimir Serbinenko | 0092c99 | 2014-08-21 01:06:53 +0200 | [diff] [blame] | 27 | #include <pc80/vga.h> |
| 28 | #include <pc80/vga_io.h> |
Arthur Heymans | 7dfc8a5 | 2016-09-02 22:35:32 +0200 | [diff] [blame] | 29 | #include <commonlib/helpers.h> |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 30 | |
Patrick Georgi | ce6e9fe | 2012-07-20 12:37:06 +0200 | [diff] [blame] | 31 | #include "i945.h" |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 32 | #include "chip.h" |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 33 | |
Patrick Georgi | 6444bd4 | 2012-07-06 11:31:39 +0200 | [diff] [blame] | 34 | #define GDRST 0xc0 |
| 35 | |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 36 | #define LVDS_CLOCK_A_POWERUP_ALL (3 << 8) |
| 37 | #define LVDS_CLOCK_B_POWERUP_ALL (3 << 4) |
| 38 | #define LVDS_CLOCK_BOTH_POWERUP_ALL (3 << 2) |
| 39 | #define DISPPLANE_BGRX888 (0x6<<26) |
| 40 | #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ |
| 41 | |
| 42 | #define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14) |
| 43 | |
| 44 | #define PGETBL_CTL 0x2020 |
| 45 | #define PGETBL_ENABLED 0x00000001 |
| 46 | |
Arthur Heymans | 7dfc8a5 | 2016-09-02 22:35:32 +0200 | [diff] [blame] | 47 | #define BASE_FREQUENCY 100000 |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 48 | |
| 49 | #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT |
| 50 | |
Francis Rowe | 71512b2 | 2015-03-16 05:31:40 +0000 | [diff] [blame] | 51 | static int gtt_setup(void *mmiobase) |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 52 | { |
| 53 | unsigned long PGETBL_save; |
Paul Menzel | cc95f18 | 2014-06-05 22:45:35 +0200 | [diff] [blame] | 54 | unsigned long tom; // top of memory |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 55 | |
Paul Menzel | cc95f18 | 2014-06-05 22:45:35 +0200 | [diff] [blame] | 56 | /* |
| 57 | * The Video BIOS places the GTT right below top of memory. |
Denis 'GNUtoo' Carikli | 16110e7 | 2014-10-14 07:33:53 +0200 | [diff] [blame] | 58 | */ |
Paul Menzel | cc95f18 | 2014-06-05 22:45:35 +0200 | [diff] [blame] | 59 | tom = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), TOLUD) << 24; |
| 60 | PGETBL_save = tom - 256 * KiB; |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 61 | PGETBL_save |= PGETBL_ENABLED; |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 62 | PGETBL_save |= 2; /* set GTT to 256kb */ |
| 63 | |
| 64 | write32(mmiobase + GFX_FLSH_CNTL, 0); |
| 65 | |
| 66 | write32(mmiobase + PGETBL_CTL, PGETBL_save); |
| 67 | |
| 68 | /* verify */ |
| 69 | if (read32(mmiobase + PGETBL_CTL) & PGETBL_ENABLED) { |
| 70 | printk(BIOS_DEBUG, "gtt_setup is enabled.\n"); |
| 71 | } else { |
| 72 | printk(BIOS_DEBUG, "gtt_setup failed!!!\n"); |
| 73 | return 1; |
| 74 | } |
| 75 | write32(mmiobase + GFX_FLSH_CNTL, 0); |
| 76 | |
| 77 | return 0; |
| 78 | } |
| 79 | |
Arthur Heymans | b59bcb2 | 2016-09-05 22:46:11 +0200 | [diff] [blame] | 80 | static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 81 | unsigned int pphysbase, unsigned int piobase, |
Francis Rowe | 71512b2 | 2015-03-16 05:31:40 +0000 | [diff] [blame] | 82 | void *pmmio, unsigned int pgfx) |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 83 | { |
| 84 | struct edid edid; |
Mono | 2e4f83b | 2015-09-07 21:15:26 +0200 | [diff] [blame] | 85 | struct edid_mode *mode; |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 86 | u8 edid_data[128]; |
| 87 | unsigned long temp; |
| 88 | int hpolarity, vpolarity; |
Arthur Heymans | 7dfc8a5 | 2016-09-02 22:35:32 +0200 | [diff] [blame] | 89 | u32 smallest_err = 0xffffffff; |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 90 | u32 target_frequency; |
| 91 | u32 pixel_p1 = 1; |
Arthur Heymans | 7dfc8a5 | 2016-09-02 22:35:32 +0200 | [diff] [blame] | 92 | u32 pixel_p2; |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 93 | u32 pixel_n = 1; |
| 94 | u32 pixel_m1 = 1; |
| 95 | u32 pixel_m2 = 1; |
| 96 | u32 hactive, vactive, right_border, bottom_border; |
| 97 | u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; |
| 98 | u32 i, j; |
| 99 | u32 uma_size; |
| 100 | u16 reg16; |
| 101 | |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 102 | printk(BIOS_SPEW, |
Francis Rowe | 71512b2 | 2015-03-16 05:31:40 +0000 | [diff] [blame] | 103 | "i915lightup: graphics %p mmio %p addrport %04x physbase %08x\n", |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 104 | (void *)pgfx, pmmio, piobase, pphysbase); |
| 105 | |
| 106 | intel_gmbus_read_edid(pmmio + GMBUS0, 3, 0x50, edid_data, 128); |
| 107 | decode_edid(edid_data, sizeof(edid_data), &edid); |
Mono | 2e4f83b | 2015-09-07 21:15:26 +0200 | [diff] [blame] | 108 | mode = &edid.mode; |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 109 | |
Mono | 2e4f83b | 2015-09-07 21:15:26 +0200 | [diff] [blame] | 110 | hpolarity = (mode->phsync == '-'); |
| 111 | vpolarity = (mode->pvsync == '-'); |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 112 | hactive = edid.x_resolution; |
| 113 | vactive = edid.y_resolution; |
Mono | 2e4f83b | 2015-09-07 21:15:26 +0200 | [diff] [blame] | 114 | right_border = mode->hborder; |
| 115 | bottom_border = mode->vborder; |
| 116 | vblank = mode->vbl; |
| 117 | hblank = mode->hbl; |
| 118 | vsync = mode->vspw; |
| 119 | hsync = mode->hspw; |
| 120 | hfront_porch = mode->hso; |
| 121 | vfront_porch = mode->vso; |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 122 | |
| 123 | for (i = 0; i < 2; i++) |
| 124 | for (j = 0; j < 0x100; j++) |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 125 | /* R = j, G = j, B = j. */ |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 126 | write32(pmmio + PALETTE(i) + 4 * j, 0x10101 * j); |
| 127 | |
| 128 | write32(pmmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS |
| 129 | | (read32(pmmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK)); |
| 130 | |
| 131 | write32(pmmio + MI_ARB_STATE, MI_ARB_C3_LP_WRITE_ENABLE | (1 << 27)); |
| 132 | /* Clean registers. */ |
| 133 | for (i = 0; i < 0x20; i += 4) |
| 134 | write32(pmmio + RENDER_RING_BASE + i, 0); |
| 135 | for (i = 0; i < 0x20; i += 4) |
| 136 | write32(pmmio + FENCE_REG_965_0 + i, 0); |
| 137 | write32(pmmio + PP_ON_DELAYS, 0); |
| 138 | write32(pmmio + PP_OFF_DELAYS, 0); |
| 139 | |
| 140 | /* Disable VGA. */ |
| 141 | write32(pmmio + VGACNTRL, VGA_DISP_DISABLE); |
| 142 | |
| 143 | /* Disable pipes. */ |
| 144 | write32(pmmio + PIPECONF(0), 0); |
| 145 | write32(pmmio + PIPECONF(1), 0); |
| 146 | |
| 147 | /* Init PRB0. */ |
| 148 | write32(pmmio + HWS_PGA, 0x352d2000); |
| 149 | write32(pmmio + PRB0_CTL, 0); |
| 150 | write32(pmmio + PRB0_HEAD, 0); |
| 151 | write32(pmmio + PRB0_TAIL, 0); |
| 152 | write32(pmmio + PRB0_START, 0); |
| 153 | write32(pmmio + PRB0_CTL, 0x0001f001); |
| 154 | |
| 155 | write32(pmmio + D_STATE, DSTATE_PLL_D3_OFF |
| 156 | | DSTATE_GFX_CLOCK_GATING | DSTATE_DOT_CLOCK_GATING); |
| 157 | write32(pmmio + ECOSKPD, 0x00010000); |
| 158 | write32(pmmio + HWSTAM, 0xeffe); |
| 159 | write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug); |
| 160 | write32(pmmio + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS); |
| 161 | |
Arthur Heymans | 7dfc8a5 | 2016-09-02 22:35:32 +0200 | [diff] [blame] | 162 | /* p2 divisor must 7 for dual channel LVDS */ |
| 163 | /* and 14 for single channel LVDS */ |
| 164 | pixel_p2 = mode->lvds_dual_channel ? 7 : 14; |
| 165 | target_frequency = mode->pixel_clock; |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 166 | |
Arthur Heymans | 7dfc8a5 | 2016-09-02 22:35:32 +0200 | [diff] [blame] | 167 | /* Find suitable divisors, m1, m2, p1, n. */ |
| 168 | /* refclock * (5 * (m1 + 2) + (m1 + 2)) / (n + 2) / p1 / p2 */ |
| 169 | /* should be closest to target frequency as possible */ |
| 170 | u32 candn, candm1, candm2, candp1; |
| 171 | for (candm1 = 8; candm1 <= 18; candm1++) { |
| 172 | for (candm2 = 3; candm2 <= 7; candm2++) { |
| 173 | for (candn = 1; candn <= 6; candn++) { |
| 174 | for (candp1 = 1; candp1 <= 8; candp1++) { |
| 175 | u32 m = 5 * (candm1 + 2) + (candm2 + 2); |
| 176 | u32 p = candp1 * pixel_p2; |
| 177 | u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUENCY * m, candn + 2); |
| 178 | u32 dot = DIV_ROUND_CLOSEST(vco, p); |
| 179 | u32 this_err = ABS(dot - target_frequency); |
| 180 | if ((m < 70) || (m > 120)) |
| 181 | continue; |
| 182 | if (this_err < smallest_err) { |
| 183 | smallest_err = this_err; |
| 184 | pixel_n = candn; |
| 185 | pixel_m1 = candm1; |
| 186 | pixel_m2 = candm2; |
| 187 | pixel_p1 = candp1; |
| 188 | } |
| 189 | } |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 190 | } |
| 191 | } |
| 192 | } |
| 193 | |
Arthur Heymans | 7dfc8a5 | 2016-09-02 22:35:32 +0200 | [diff] [blame] | 194 | if (smallest_err == 0xffffffff) { |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 195 | printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); |
| 196 | return -1; |
| 197 | } |
| 198 | |
| 199 | printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", |
| 200 | hactive, vactive); |
| 201 | printk(BIOS_DEBUG, "Borders %d x %d\n", right_border, bottom_border); |
| 202 | printk(BIOS_DEBUG, "Blank %d x %d\n", hblank, vblank); |
| 203 | printk(BIOS_DEBUG, "Sync %d x %d\n", hsync, vsync); |
| 204 | printk(BIOS_DEBUG, "Front porch %d x %d\n", hfront_porch, vfront_porch); |
| 205 | printk(BIOS_DEBUG, (conf->gpu_lvds_use_spread_spectrum_clock |
| 206 | ? "Spread spectrum clock\n" |
| 207 | : "DREF clock\n")); |
Vladimir Serbinenko | 551cff0 | 2015-10-10 23:58:08 +0200 | [diff] [blame] | 208 | printk(BIOS_DEBUG, (mode->lvds_dual_channel |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 209 | ? "Dual channel\n" |
| 210 | : "Single channel\n")); |
| 211 | printk(BIOS_DEBUG, "Polarities %d, %d\n", |
| 212 | hpolarity, vpolarity); |
| 213 | printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", |
| 214 | pixel_n, pixel_m1, pixel_m2, pixel_p1); |
| 215 | printk(BIOS_DEBUG, "Pixel clock %d kHz\n", |
Arthur Heymans | 7dfc8a5 | 2016-09-02 22:35:32 +0200 | [diff] [blame] | 216 | BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / |
| 217 | (pixel_n + 2) / (pixel_p1 * pixel_p2)); |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 218 | |
Vladimir Serbinenko | 0092c99 | 2014-08-21 01:06:53 +0200 | [diff] [blame] | 219 | #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) |
| 220 | write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); |
| 221 | write32(pmmio + PF_WIN_POS(0), 0); |
| 222 | write32(pmmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); |
| 223 | write32(pmmio + PFIT_CONTROL, PFIT_ENABLE | (1 << PFIT_PIPE_SHIFT) | HORIZ_AUTO_SCALE | VERT_AUTO_SCALE); |
| 224 | #else |
| 225 | /* Disable panel fitter (we're in native resolution). */ |
| 226 | write32(pmmio + PF_CTL(0), 0); |
| 227 | write32(pmmio + PF_WIN_SZ(0), 0); |
| 228 | write32(pmmio + PF_WIN_POS(0), 0); |
| 229 | write32(pmmio + PFIT_PGM_RATIOS, 0); |
| 230 | write32(pmmio + PFIT_CONTROL, 0); |
| 231 | #endif |
| 232 | |
| 233 | mdelay(1); |
| 234 | |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 235 | write32(pmmio + DSPCNTR(0), DISPPLANE_BGRX888 |
| 236 | | DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE); |
| 237 | |
| 238 | mdelay(1); |
| 239 | write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS |
| 240 | | (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); |
| 241 | write32(pmmio + FP0(1), |
Arthur Heymans | 7dfc8a5 | 2016-09-02 22:35:32 +0200 | [diff] [blame] | 242 | (pixel_n << 16) |
| 243 | | (pixel_m1 << 8) | pixel_m2); |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 244 | write32(pmmio + DPLL(1), |
| 245 | DPLL_VGA_MODE_DIS | |
| 246 | DPLL_VCO_ENABLE | DPLLB_MODE_LVDS |
Vladimir Serbinenko | 551cff0 | 2015-10-10 23:58:08 +0200 | [diff] [blame] | 247 | | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 248 | : DPLLB_LVDS_P2_CLOCK_DIV_14) |
| 249 | | (conf->gpu_lvds_use_spread_spectrum_clock |
| 250 | ? DPLL_INTEGRATED_CLOCK_VLV | DPLL_INTEGRATED_CRI_CLK_VLV |
| 251 | : 0) |
Arthur Heymans | 7dfc8a5 | 2016-09-02 22:35:32 +0200 | [diff] [blame] | 252 | | (0x10000 << (pixel_p1 - 1))); |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 253 | mdelay(1); |
| 254 | write32(pmmio + DPLL(1), |
| 255 | DPLL_VGA_MODE_DIS | |
| 256 | DPLL_VCO_ENABLE | DPLLB_MODE_LVDS |
Vladimir Serbinenko | 551cff0 | 2015-10-10 23:58:08 +0200 | [diff] [blame] | 257 | | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 258 | : DPLLB_LVDS_P2_CLOCK_DIV_14) |
| 259 | | ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13) |
Arthur Heymans | 7dfc8a5 | 2016-09-02 22:35:32 +0200 | [diff] [blame] | 260 | | (0x10000 << (pixel_p1 - 1))); |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 261 | mdelay(1); |
| 262 | write32(pmmio + HTOTAL(1), |
| 263 | ((hactive + right_border + hblank - 1) << 16) |
| 264 | | (hactive - 1)); |
| 265 | write32(pmmio + HBLANK(1), |
| 266 | ((hactive + right_border + hblank - 1) << 16) |
| 267 | | (hactive + right_border - 1)); |
| 268 | write32(pmmio + HSYNC(1), |
| 269 | ((hactive + right_border + hfront_porch + hsync - 1) << 16) |
| 270 | | (hactive + right_border + hfront_porch - 1)); |
| 271 | |
| 272 | write32(pmmio + VTOTAL(1), ((vactive + bottom_border + vblank - 1) << 16) |
| 273 | | (vactive - 1)); |
| 274 | write32(pmmio + VBLANK(1), ((vactive + bottom_border + vblank - 1) << 16) |
| 275 | | (vactive + bottom_border - 1)); |
| 276 | write32(pmmio + VSYNC(1), |
| 277 | (vactive + bottom_border + vfront_porch + vsync - 1) |
| 278 | | (vactive + bottom_border + vfront_porch - 1)); |
| 279 | |
Vladimir Serbinenko | 0092c99 | 2014-08-21 01:06:53 +0200 | [diff] [blame] | 280 | #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) |
| 281 | write32(pmmio + PIPESRC(1), (639 << 16) | 399); |
| 282 | #else |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 283 | write32(pmmio + PIPESRC(1), ((hactive - 1) << 16) | (vactive - 1)); |
Vladimir Serbinenko | 0092c99 | 2014-08-21 01:06:53 +0200 | [diff] [blame] | 284 | #endif |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 285 | mdelay(1); |
| 286 | |
| 287 | write32(pmmio + DSPSIZE(0), (hactive - 1) | ((vactive - 1) << 16)); |
| 288 | write32(pmmio + DSPPOS(0), 0); |
| 289 | |
| 290 | /* Backlight init. */ |
| 291 | write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); |
| 292 | write32(pmmio + FW_BLC, 0x011d011a); |
| 293 | write32(pmmio + FW_BLC2, 0x00000102); |
| 294 | write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); |
| 295 | write32(pmmio + FW_BLC_SELF, 0x0001003f); |
| 296 | write32(pmmio + FW_BLC, 0x011d0109); |
| 297 | write32(pmmio + FW_BLC2, 0x00000102); |
| 298 | write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); |
| 299 | write32(pmmio + BLC_PWM_CTL, conf->gpu_backlight); |
| 300 | |
| 301 | edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; |
| 302 | write32(pmmio + DSPADDR(0), 0); |
| 303 | write32(pmmio + DSPSURF(0), 0); |
| 304 | write32(pmmio + DSPSTRIDE(0), edid.bytes_per_line); |
| 305 | write32(pmmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888 |
| 306 | | DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE); |
| 307 | mdelay(1); |
| 308 | |
| 309 | write32(pmmio + PIPECONF(1), PIPECONF_ENABLE); |
| 310 | write32(pmmio + LVDS, LVDS_ON |
| 311 | | (hpolarity << 20) | (vpolarity << 21) |
Vladimir Serbinenko | 551cff0 | 2015-10-10 23:58:08 +0200 | [diff] [blame] | 312 | | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 313 | | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) |
| 314 | | LVDS_CLOCK_A_POWERUP_ALL |
| 315 | | LVDS_PIPE(1)); |
| 316 | |
| 317 | write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); |
| 318 | write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET); |
| 319 | mdelay(1); |
| 320 | write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS |
| 321 | | PANEL_POWER_ON | PANEL_POWER_RESET); |
| 322 | |
| 323 | printk (BIOS_DEBUG, "waiting for panel powerup\n"); |
| 324 | while (1) { |
| 325 | u32 reg32; |
| 326 | reg32 = read32(pmmio + PP_STATUS); |
| 327 | if ((reg32 & PP_SEQUENCE_MASK) == PP_SEQUENCE_NONE) |
| 328 | break; |
| 329 | } |
| 330 | printk (BIOS_DEBUG, "panel powered up\n"); |
| 331 | |
| 332 | write32(pmmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); |
| 333 | |
| 334 | /* Clear interrupts. */ |
| 335 | write32(pmmio + DEIIR, 0xffffffff); |
| 336 | write32(pmmio + SDEIIR, 0xffffffff); |
| 337 | write32(pmmio + IIR, 0xffffffff); |
| 338 | write32(pmmio + IMR, 0xffffffff); |
| 339 | write32(pmmio + EIR, 0xffffffff); |
| 340 | |
| 341 | if (gtt_setup(pmmio)) { |
| 342 | printk(BIOS_ERR, "ERROR: GTT Setup Failed!!!\n"); |
| 343 | return 0; |
| 344 | } |
| 345 | |
| 346 | /* Setup GTT. */ |
| 347 | |
| 348 | reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); |
| 349 | uma_size = 0; |
| 350 | if (!(reg16 & 2)) { |
Arthur Heymans | 874a8f9 | 2016-05-19 16:06:09 +0200 | [diff] [blame] | 351 | uma_size = decode_igd_memory_size((reg16 >> 4) & 7); |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 352 | printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); |
| 353 | } |
| 354 | |
Vladimir Serbinenko | 055fe03 | 2014-08-19 23:59:27 +0200 | [diff] [blame] | 355 | for (i = 0; i < (uma_size - 256) / 4; i++) |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 356 | { |
| 357 | outl((i << 2) | 1, piobase); |
| 358 | outl(pphysbase + (i << 12) + 1, piobase + 4); |
| 359 | } |
| 360 | |
| 361 | temp = read32(pmmio + PGETBL_CTL); |
| 362 | printk(BIOS_INFO, "GTT PGETBL_CTL register: 0x%lx\n", temp); |
| 363 | |
| 364 | if (temp & 1) |
| 365 | printk(BIOS_INFO, "GTT Enabled\n"); |
| 366 | else |
| 367 | printk(BIOS_ERR, "ERROR: GTT is still Disabled!!!\n"); |
| 368 | |
Vladimir Serbinenko | 0092c99 | 2014-08-21 01:06:53 +0200 | [diff] [blame] | 369 | #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) |
| 370 | vga_misc_write(0x67); |
| 371 | |
| 372 | write32(pmmio + DSPCNTR(0), DISPPLANE_SEL_PIPE_B); |
| 373 | |
| 374 | write32(pmmio + VGACNTRL, 0x02c4008e | VGA_PIPE_B_SELECT); |
| 375 | |
| 376 | vga_textmode_init(); |
| 377 | #else |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 378 | printk(BIOS_SPEW, "memset %p to 0x00 for %d bytes\n", |
| 379 | (void *)pgfx, hactive * vactive * 4); |
| 380 | memset((void *)pgfx, 0x00, hactive * vactive * 4); |
| 381 | |
| 382 | set_vbe_mode_info_valid(&edid, pgfx); |
Vladimir Serbinenko | 0092c99 | 2014-08-21 01:06:53 +0200 | [diff] [blame] | 383 | #endif |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 384 | return 0; |
| 385 | } |
Arthur Heymans | b59bcb2 | 2016-09-05 22:46:11 +0200 | [diff] [blame] | 386 | |
| 387 | static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf, |
| 388 | unsigned int pphysbase, unsigned int piobase, |
| 389 | void *pmmio, unsigned int pgfx) |
| 390 | { |
| 391 | int i; |
| 392 | u32 hactive, vactive; |
| 393 | u16 reg16; |
| 394 | u32 uma_size; |
| 395 | |
| 396 | printk(BIOS_SPEW, "pmmio %x addrport %x physbase %x\n", |
| 397 | (u32)pmmio, piobase, pphysbase); |
| 398 | |
| 399 | gtt_setup(pmmio); |
| 400 | |
| 401 | /* Disable VGA. */ |
| 402 | write32(pmmio + VGACNTRL, VGA_DISP_DISABLE); |
| 403 | |
| 404 | /* Disable pipes. */ |
| 405 | write32(pmmio + PIPECONF(0), 0); |
| 406 | write32(pmmio + PIPECONF(1), 0); |
| 407 | |
| 408 | write32(pmmio + INSTPM, 0x800); |
| 409 | |
| 410 | vga_gr_write(0x18, 0); |
| 411 | |
| 412 | write32(pmmio + VGA0, 0x200074); |
| 413 | write32(pmmio + VGA1, 0x200074); |
| 414 | |
| 415 | write32(pmmio + DSPFW3, 0x7f3f00c1 & ~PINEVIEW_SELF_REFRESH_EN); |
| 416 | write32(pmmio + DSPCLK_GATE_D, 0); |
| 417 | write32(pmmio + FW_BLC, 0x03060106); |
| 418 | write32(pmmio + FW_BLC2, 0x00000306); |
| 419 | |
| 420 | write32(pmmio + ADPA, ADPA_DAC_ENABLE |
| 421 | | ADPA_PIPE_A_SELECT |
| 422 | | ADPA_USE_VGA_HVPOLARITY |
| 423 | | ADPA_VSYNC_CNTL_ENABLE |
| 424 | | ADPA_HSYNC_CNTL_ENABLE |
| 425 | | ADPA_DPMS_ON |
| 426 | ); |
| 427 | |
| 428 | write32(pmmio + 0x7041c, 0x0); |
| 429 | |
| 430 | write32(pmmio + DPLL_MD(0), 0x3); |
| 431 | write32(pmmio + DPLL_MD(1), 0x3); |
| 432 | write32(pmmio + DSPCNTR(1), 0x1000000); |
| 433 | write32(pmmio + PIPESRC(1), 0x027f01df); |
| 434 | |
| 435 | vga_misc_write(0x67); |
| 436 | const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, |
| 437 | 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, |
| 438 | 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, |
| 439 | 0xff |
| 440 | }; |
| 441 | vga_cr_write(0x11, 0); |
| 442 | |
| 443 | for (i = 0; i <= 0x18; i++) |
| 444 | vga_cr_write(i, cr[i]); |
| 445 | |
| 446 | // Disable screen memory to prevent garbage from appearing. |
| 447 | vga_sr_write(1, vga_sr_read(1) | 0x20); |
| 448 | hactive = 640; |
| 449 | vactive = 400; |
| 450 | |
| 451 | mdelay(1); |
| 452 | write32(pmmio + DPLL(0), |
| 453 | DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL |
| 454 | | DPLL_VGA_MODE_DIS |
| 455 | | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 |
| 456 | | 0x400601 |
| 457 | ); |
| 458 | mdelay(1); |
| 459 | write32(pmmio + DPLL(0), |
| 460 | DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL |
| 461 | | DPLL_VGA_MODE_DIS |
| 462 | | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 |
| 463 | | 0x400601 |
| 464 | ); |
| 465 | |
| 466 | write32(pmmio + ADPA, ADPA_DAC_ENABLE |
| 467 | | ADPA_PIPE_A_SELECT |
| 468 | | ADPA_USE_VGA_HVPOLARITY |
| 469 | | ADPA_VSYNC_CNTL_ENABLE |
| 470 | | ADPA_HSYNC_CNTL_ENABLE |
| 471 | | ADPA_DPMS_ON |
| 472 | ); |
| 473 | |
| 474 | write32(pmmio + HTOTAL(0), |
| 475 | ((hactive - 1) << 16) |
| 476 | | (hactive - 1)); |
| 477 | write32(pmmio + HBLANK(0), |
| 478 | ((hactive - 1) << 16) |
| 479 | | (hactive - 1)); |
| 480 | write32(pmmio + HSYNC(0), |
| 481 | ((hactive - 1) << 16) |
| 482 | | (hactive - 1)); |
| 483 | |
| 484 | write32(pmmio + VTOTAL(0), ((vactive - 1) << 16) |
| 485 | | (vactive - 1)); |
| 486 | write32(pmmio + VBLANK(0), ((vactive - 1) << 16) |
| 487 | | (vactive - 1)); |
| 488 | write32(pmmio + VSYNC(0), |
| 489 | ((vactive - 1) << 16) |
| 490 | | (vactive - 1)); |
| 491 | |
| 492 | write32(pmmio + PF_WIN_POS(0), 0); |
| 493 | |
| 494 | write32(pmmio + PIPESRC(0), (639 << 16) | 399); |
| 495 | write32(pmmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); |
| 496 | write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); |
| 497 | write32(pmmio + PFIT_CONTROL, 0x0); |
| 498 | |
| 499 | mdelay(1); |
| 500 | |
| 501 | write32(pmmio + FDI_RX_CTL(0), 0x00002040); |
| 502 | mdelay(1); |
| 503 | write32(pmmio + FDI_RX_CTL(0), 0x80002050); |
| 504 | write32(pmmio + FDI_TX_CTL(0), 0x00044000); |
| 505 | mdelay(1); |
| 506 | write32(pmmio + FDI_TX_CTL(0), 0x80044000); |
| 507 | write32(pmmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); |
| 508 | |
| 509 | write32(pmmio + VGACNTRL, 0x0); |
| 510 | write32(pmmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); |
| 511 | mdelay(1); |
| 512 | |
| 513 | write32(pmmio + ADPA, ADPA_DAC_ENABLE |
| 514 | | ADPA_PIPE_A_SELECT |
| 515 | | ADPA_USE_VGA_HVPOLARITY |
| 516 | | ADPA_VSYNC_CNTL_ENABLE |
| 517 | | ADPA_HSYNC_CNTL_ENABLE |
| 518 | | ADPA_DPMS_ON |
| 519 | ); |
| 520 | |
| 521 | write32(pmmio + DSPFW3, 0x7f3f00c1); |
| 522 | write32(pmmio + MI_MODE, 0x200 | VS_TIMER_DISPATCH); |
| 523 | write32(pmmio + CACHE_MODE_0, (0x6820 | (1 << 9)) & ~(1 << 5)); |
| 524 | write32(pmmio + CACHE_MODE_1, 0x380 & ~(1 << 9)); |
| 525 | |
| 526 | /* Set up GTT. */ |
| 527 | |
| 528 | reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); |
| 529 | uma_size = 0; |
| 530 | if (!(reg16 & 2)) { |
| 531 | uma_size = decode_igd_memory_size((reg16 >> 4) & 7); |
| 532 | printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); |
| 533 | } |
| 534 | |
| 535 | for (i = 0; i < (uma_size - 256) / 4; i++) |
| 536 | { |
| 537 | outl((i << 2) | 1, piobase); |
| 538 | outl(pphysbase + (i << 12) + 1, piobase + 4); |
| 539 | } |
| 540 | |
| 541 | /* Clear interrupts. */ |
| 542 | write32(pmmio + DEIIR, 0xffffffff); |
| 543 | write32(pmmio + SDEIIR, 0xffffffff); |
| 544 | write32(pmmio + IIR, 0xffffffff); |
| 545 | write32(pmmio + IMR, 0xffffffff); |
| 546 | write32(pmmio + EIR, 0xffffffff); |
| 547 | |
| 548 | vga_textmode_init(); |
| 549 | |
| 550 | /* Enable screen memory. */ |
| 551 | vga_sr_write(1, vga_sr_read(1) & ~0x20); |
| 552 | |
| 553 | return 0; |
| 554 | |
| 555 | } |
| 556 | |
| 557 | /* compare the header of the vga edid header */ |
| 558 | /* if vga is not connected it should have a correct header */ |
| 559 | static int vga_connected(u8 *pmmio) { |
| 560 | u8 vga_edid[128]; |
| 561 | u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; |
| 562 | intel_gmbus_read_edid(pmmio + GMBUS0, 2, 0x50, vga_edid, 128); |
| 563 | intel_gmbus_stop(pmmio + GMBUS0); |
| 564 | for (int i = 0; i < 8; i++) { |
| 565 | if (vga_edid[i] != header[i]) { |
| 566 | printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); |
| 567 | return 0; |
| 568 | } |
| 569 | } |
| 570 | printk(BIOS_SPEW, "VGA display connected\n"); |
| 571 | return 1; |
| 572 | } |
| 573 | |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 574 | #endif |
| 575 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 576 | static void gma_func0_init(struct device *dev) |
| 577 | { |
| 578 | u32 reg32; |
| 579 | |
Patrick Georgi | 6444bd4 | 2012-07-06 11:31:39 +0200 | [diff] [blame] | 580 | /* Unconditionally reset graphics */ |
| 581 | pci_write_config8(dev, GDRST, 1); |
| 582 | udelay(50); |
| 583 | pci_write_config8(dev, GDRST, 0); |
| 584 | /* wait for device to finish */ |
| 585 | while (pci_read_config8(dev, GDRST) & 1) { }; |
| 586 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 587 | /* IGD needs to be Bus Master */ |
| 588 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 589 | pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER |
| 590 | | PCI_COMMAND_IO | PCI_COMMAND_MEMORY); |
Denis 'GNUtoo' Carikli | ed7e29e | 2013-02-24 12:01:44 +0100 | [diff] [blame] | 591 | |
| 592 | #if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT |
| 593 | /* PCI Init, will run VBIOS */ |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 594 | pci_dev_init(dev); |
Denis 'GNUtoo' Carikli | ed7e29e | 2013-02-24 12:01:44 +0100 | [diff] [blame] | 595 | #endif |
| 596 | |
| 597 | |
| 598 | #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT |
| 599 | /* This should probably run before post VBIOS init. */ |
| 600 | printk(BIOS_SPEW, "Initializing VGA without OPROM.\n"); |
Francis Rowe | 71512b2 | 2015-03-16 05:31:40 +0000 | [diff] [blame] | 601 | void *mmiobase; |
| 602 | u32 iobase, graphics_base; |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 603 | struct northbridge_intel_i945_config *conf = dev->chip_info; |
| 604 | |
Denis 'GNUtoo' Carikli | ed7e29e | 2013-02-24 12:01:44 +0100 | [diff] [blame] | 605 | iobase = dev->resource_list[1].base; |
Francis Rowe | 71512b2 | 2015-03-16 05:31:40 +0000 | [diff] [blame] | 606 | mmiobase = (void *)(uintptr_t)dev->resource_list[0].base; |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 607 | graphics_base = dev->resource_list[2].base; |
Denis 'GNUtoo' Carikli | ed7e29e | 2013-02-24 12:01:44 +0100 | [diff] [blame] | 608 | |
Elyes HAOUAS | 0a15fe9 | 2016-09-17 19:12:27 +0200 | [diff] [blame] | 609 | printk(BIOS_SPEW, "GMADR = 0x%08x GTTADR = 0x%08x\n", |
Paul Menzel | d235da1 | 2014-06-03 00:15:30 +0200 | [diff] [blame] | 610 | pci_read_config32(dev, GMADR), |
| 611 | pci_read_config32(dev, GTTADR) |
Peter Stuge | c6f0997 | 2013-06-08 01:31:44 +0200 | [diff] [blame] | 612 | ); |
| 613 | |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 614 | int err; |
Arthur Heymans | b59bcb2 | 2016-09-05 22:46:11 +0200 | [diff] [blame] | 615 | if (vga_connected(mmiobase)) |
| 616 | err = intel_gma_init_vga(conf, pci_read_config32(dev, 0x5c) & ~0xf, |
| 617 | iobase, mmiobase, graphics_base); |
| 618 | else |
| 619 | err = intel_gma_init_lvds(conf, pci_read_config32(dev, 0x5c) & ~0xf, |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 620 | iobase, mmiobase, graphics_base); |
| 621 | if (err == 0) |
Kyösti Mälkki | ab56b3b | 2013-11-28 16:44:51 +0200 | [diff] [blame] | 622 | gfx_set_init_done(1); |
Arthur Heymans | 333176e | 2016-09-07 22:10:57 +0200 | [diff] [blame] | 623 | /* Linux relies on VBT for panel info. */ |
| 624 | if (CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) { |
| 625 | generate_fake_intel_oprom(&conf->gfx, dev, |
| 626 | "$VBT CALISTOGA"); |
| 627 | } |
| 628 | if (CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC) { |
| 629 | generate_fake_intel_oprom(&conf->gfx, dev, |
| 630 | "$VBT LAKEPORT-G"); |
| 631 | } |
Denis 'GNUtoo' Carikli | ed7e29e | 2013-02-24 12:01:44 +0100 | [diff] [blame] | 632 | #endif |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 633 | } |
| 634 | |
Patrick Georgi | ce6e9fe | 2012-07-20 12:37:06 +0200 | [diff] [blame] | 635 | /* This doesn't reclaim stolen UMA memory, but IGD could still |
| 636 | be reenabled later. */ |
| 637 | static void gma_func0_disable(struct device *dev) |
| 638 | { |
| 639 | struct device *dev_host = dev_find_slot(0, PCI_DEVFN(0x0, 0)); |
| 640 | |
| 641 | pci_write_config16(dev, GCFC, 0xa00); |
| 642 | pci_write_config16(dev_host, GGC, (1 << 1)); |
| 643 | |
| 644 | unsigned int reg32 = pci_read_config32(dev_host, DEVEN); |
| 645 | reg32 &= ~(DEVEN_D2F0 | DEVEN_D2F1); |
| 646 | pci_write_config32(dev_host, DEVEN, reg32); |
| 647 | |
| 648 | dev->enabled = 0; |
| 649 | } |
| 650 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 651 | static void gma_func1_init(struct device *dev) |
| 652 | { |
| 653 | u32 reg32; |
Alexander Couzens | c7a1a3e | 2016-03-09 10:42:58 +0100 | [diff] [blame] | 654 | u8 val; |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 655 | |
| 656 | /* IGD needs to be Bus Master, also enable IO accesss */ |
| 657 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
Stefan Reinauer | 109ab31 | 2009-08-12 16:08:05 +0000 | [diff] [blame] | 658 | pci_write_config32(dev, PCI_COMMAND, reg32 | |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 659 | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
Sven Schnelle | b629d14 | 2011-06-12 14:30:10 +0200 | [diff] [blame] | 660 | |
Alexander Couzens | c7a1a3e | 2016-03-09 10:42:58 +0100 | [diff] [blame] | 661 | if (get_option(&val, "tft_brightness") == CB_SUCCESS) |
| 662 | pci_write_config8(dev, 0xf4, val); |
| 663 | else |
| 664 | pci_write_config8(dev, 0xf4, 0xff); |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 665 | } |
| 666 | |
| 667 | static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) |
| 668 | { |
| 669 | if (!vendor || !device) { |
| 670 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 671 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 672 | } else { |
| 673 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 674 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 675 | } |
| 676 | } |
| 677 | |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 678 | const struct i915_gpu_controller_info * |
| 679 | intel_gma_get_controller_info(void) |
| 680 | { |
| 681 | device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0)); |
| 682 | if (!dev) { |
| 683 | return NULL; |
| 684 | } |
| 685 | struct northbridge_intel_i945_config *chip = dev->chip_info; |
Patrick Georgi | 54e227e | 2015-08-08 22:02:12 +0200 | [diff] [blame] | 686 | if (!chip) { |
| 687 | return NULL; |
| 688 | } |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 689 | return &chip->gfx; |
| 690 | } |
| 691 | |
Alexander Couzens | 5eea458 | 2015-04-12 22:18:55 +0200 | [diff] [blame] | 692 | static void gma_ssdt(device_t device) |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 693 | { |
| 694 | const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); |
| 695 | if (!gfx) { |
| 696 | return; |
| 697 | } |
| 698 | |
| 699 | drivers_intel_gma_displays_ssdt_generate(gfx); |
| 700 | } |
| 701 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 702 | static struct pci_operations gma_pci_ops = { |
| 703 | .set_subsystem = gma_set_subsystem, |
| 704 | }; |
| 705 | |
| 706 | static struct device_operations gma_func0_ops = { |
| 707 | .read_resources = pci_dev_read_resources, |
| 708 | .set_resources = pci_dev_set_resources, |
| 709 | .enable_resources = pci_dev_enable_resources, |
| 710 | .init = gma_func0_init, |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 711 | .acpi_fill_ssdt_generator = gma_ssdt, |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 712 | .scan_bus = 0, |
| 713 | .enable = 0, |
Patrick Georgi | ce6e9fe | 2012-07-20 12:37:06 +0200 | [diff] [blame] | 714 | .disable = gma_func0_disable, |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 715 | .ops_pci = &gma_pci_ops, |
| 716 | }; |
| 717 | |
| 718 | |
| 719 | static struct device_operations gma_func1_ops = { |
| 720 | .read_resources = pci_dev_read_resources, |
| 721 | .set_resources = pci_dev_set_resources, |
| 722 | .enable_resources = pci_dev_enable_resources, |
| 723 | .init = gma_func1_init, |
| 724 | .scan_bus = 0, |
| 725 | .enable = 0, |
| 726 | .ops_pci = &gma_pci_ops, |
| 727 | }; |
| 728 | |
Arthur Heymans | 0b9ecb5 | 2016-09-06 23:03:04 +0200 | [diff] [blame] | 729 | static const unsigned short pci_device_ids[] = { 0x27a2, 0x27ae, 0x2772, 0 }; |
Vladimir Serbinenko | 10dd0e3 | 2014-11-17 00:07:12 +0100 | [diff] [blame] | 730 | |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 731 | static const struct pci_driver i945_gma_func0_driver __pci_driver = { |
| 732 | .ops = &gma_func0_ops, |
| 733 | .vendor = PCI_VENDOR_ID_INTEL, |
Vladimir Serbinenko | 10dd0e3 | 2014-11-17 00:07:12 +0100 | [diff] [blame] | 734 | .devices = pci_device_ids, |
Stefan Reinauer | 30140a5 | 2009-03-11 16:20:39 +0000 | [diff] [blame] | 735 | }; |
| 736 | |
| 737 | static const struct pci_driver i945_gma_func1_driver __pci_driver = { |
| 738 | .ops = &gma_func1_ops, |
| 739 | .vendor = PCI_VENDOR_ID_INTEL, |
| 740 | .device = 0x27a6, |
| 741 | }; |