Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Dave Frodin | 2093c4f | 2014-06-13 08:12:48 -0600 | [diff] [blame] | 2 | |
| 3 | #ifndef _AMD_FAM15TN_PCI_DEVS_H_ |
| 4 | #define _AMD_FAM15TN_PCI_DEVS_H_ |
| 5 | |
Kyösti Mälkki | f7ca672 | 2017-09-10 06:30:54 +0300 | [diff] [blame] | 6 | #include <device/pci_def.h> |
| 7 | |
Dave Frodin | 2093c4f | 2014-06-13 08:12:48 -0600 | [diff] [blame] | 8 | #define BUS0 0 |
| 9 | |
Mike Banon | 1e6a227 | 2020-11-21 21:58:50 +0300 | [diff] [blame] | 10 | /* GNB Root Complex */ |
| 11 | #define GNB_DEV 0x0 |
| 12 | #define GNB_FUNC 0 |
| 13 | #define GNB_DEVFN PCI_DEVFN(GNB_DEV, GNB_FUNC) |
| 14 | |
| 15 | /* IOMMU */ |
| 16 | #define IOMMU_DEV 0x0 |
| 17 | #define IOMMU_FUNC 2 |
| 18 | #define IOMMU_DEVFN PCI_DEVFN(IOMMU_DEV, IOMMU_FUNC) |
| 19 | |
Dave Frodin | 2093c4f | 2014-06-13 08:12:48 -0600 | [diff] [blame] | 20 | /* Graphics and Display */ |
| 21 | #define GFX_DEV 0x1 |
| 22 | #define GFX_FUNC 0 |
Elyes Haouas | 693f7c1 | 2022-07-16 09:38:17 +0200 | [diff] [blame] | 23 | #define GFX_DEVFN PCI_DEVFN(GFX_DEV, GFX_FUNC) |
Dave Frodin | 2093c4f | 2014-06-13 08:12:48 -0600 | [diff] [blame] | 24 | |
Mike Banon | 58d0336 | 2020-10-20 15:31:17 +0300 | [diff] [blame] | 25 | /* Integrated GPU Internal HDMI Audio Controller */ |
| 26 | #define ACTL_FUNC 1 |
Elyes Haouas | 693f7c1 | 2022-07-16 09:38:17 +0200 | [diff] [blame] | 27 | #define ACTL_DEVFN PCI_DEVFN(GFX_DEV, ACTL_FUNC) |
Mike Banon | 58d0336 | 2020-10-20 15:31:17 +0300 | [diff] [blame] | 28 | |
Dave Frodin | 2093c4f | 2014-06-13 08:12:48 -0600 | [diff] [blame] | 29 | /* PCIe Ports */ |
| 30 | #define NB_PCIE_PORT1_DEV 0x2 |
| 31 | #define NB_PCIE_PORT2_DEV 0x3 |
| 32 | #define NB_PCIE_PORT3_DEV 0x4 |
| 33 | #define NB_PCIE_PORT4_DEV 0x5 |
| 34 | #define NB_PCIE_PORT5_DEV 0x6 |
| 35 | #define NB_PCIE_PORT6_DEV 0x7 |
| 36 | #define NB_PCIE_PORT7_DEV 0x8 |
| 37 | #define NB_PCIE_FUNC 0 |
| 38 | #define NB_PCIE_PORT1_DEVID 0x1412 |
| 39 | #define NB_PCIE_PORT2_DEVID 0x1413 |
| 40 | #define NB_PCIE_PORT3_DEVID 0x1414 |
| 41 | #define NB_PCIE_PORT4_DEVID 0x1415 |
| 42 | #define NB_PCIE_PORT5_DEVID 0x1416 |
| 43 | #define NB_PCIE_PORT6_DEVID 0x1417 |
| 44 | #define NB_PCIE_PORT7_DEVID 0x1418 |
Elyes Haouas | 693f7c1 | 2022-07-16 09:38:17 +0200 | [diff] [blame] | 45 | #define NB_PCIE_PORT1_DEVFN PCI_DEVFN(NB_PCIE_PORT1_DEV, NB_PCIE_FUNC) |
| 46 | #define NB_PCIE_PORT2_DEVFN PCI_DEVFN(NB_PCIE_PORT2_DEV, NB_PCIE_FUNC) |
| 47 | #define NB_PCIE_PORT3_DEVFN PCI_DEVFN(NB_PCIE_PORT3_DEV, NB_PCIE_FUNC) |
| 48 | #define NB_PCIE_PORT4_DEVFN PCI_DEVFN(NB_PCIE_PORT4_DEV, NB_PCIE_FUNC) |
| 49 | #define NB_PCIE_PORT5_DEVFN PCI_DEVFN(NB_PCIE_PORT5_DEV, NB_PCIE_FUNC) |
| 50 | #define NB_PCIE_PORT6_DEVFN PCI_DEVFN(NB_PCIE_PORT6_DEV, NB_PCIE_FUNC) |
| 51 | #define NB_PCIE_PORT7_DEVFN PCI_DEVFN(NB_PCIE_PORT7_DEV, NB_PCIE_FUNC) |
Dave Frodin | 2093c4f | 2014-06-13 08:12:48 -0600 | [diff] [blame] | 52 | |
| 53 | #endif /* _AMD_FAM15TN_PCI_DEVS_H_ */ |