Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 1 | # |
| 2 | # This file is part of the coreboot project. |
| 3 | # |
| 4 | # Copyright (C) 2011 Advanced Micro Devices, Inc. |
Edward O'Callaghan | 6e56de3 | 2014-01-25 21:46:10 +1100 | [diff] [blame] | 5 | # Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>. |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 6 | # |
| 7 | # This program is free software; you can redistribute it and/or modify |
| 8 | # it under the terms of the GNU General Public License as published by |
| 9 | # the Free Software Foundation; version 2 of the License. |
| 10 | # |
| 11 | # This program is distributed in the hope that it will be useful, |
| 12 | # but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | # GNU General Public License for more details. |
| 15 | # |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 16 | chip northbridge/amd/agesa/family14/root_complex |
| 17 | device cpu_cluster 0 on |
| 18 | chip cpu/amd/agesa/family14 |
Edward O'Callaghan | bbe3e44 | 2014-05-02 03:11:42 +1000 | [diff] [blame] | 19 | device lapic 0 on end |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 20 | end |
| 21 | end |
| 22 | device domain 0 on |
| 23 | subsystemid 0x1022 0x1510 inherit |
| 24 | chip northbridge/amd/agesa/family14 # CPU side of HT root complex |
| 25 | # device pci 18.0 on # northbridge |
| 26 | chip northbridge/amd/agesa/family14 # PCI side of HT root complex |
| 27 | device pci 0.0 on end # Root Complex |
| 28 | device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456] |
Edward O'Callaghan | 6e56de3 | 2014-01-25 21:46:10 +1100 | [diff] [blame] | 29 | # device pci 1.1 on end # Internal Audio P2P bridge 0x1314 |
Edward O'Callaghan | 93fa422 | 2014-03-04 23:54:16 +1100 | [diff] [blame] | 30 | device pci 4.0 on end # PCIE P2P bridge PCIe slot |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 31 | device pci 5.0 off end # PCIE P2P bridge |
Edward O'Callaghan | 93fa422 | 2014-03-04 23:54:16 +1100 | [diff] [blame] | 32 | device pci 6.0 on end # GbE MAC: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 (10ec:8168) |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 33 | device pci 7.0 off end # PCIE P2P bridge |
| 34 | device pci 8.0 off end # NB/SB Link P2P bridge |
| 35 | end # agesa northbridge |
| 36 | |
| 37 | chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus |
| 38 | device pci 11.0 on end # SATA |
| 39 | device pci 12.0 on end # OHCI USB 0-4 |
| 40 | device pci 12.2 on end # EHCI USB 0-4 |
| 41 | device pci 13.0 on end # OHCI USB 5-9 |
| 42 | device pci 13.2 on end # EHCI USB 5-9 |
| 43 | device pci 14.0 on # SM |
Edward O'Callaghan | bbe3e44 | 2014-05-02 03:11:42 +1000 | [diff] [blame] | 44 | chip drivers/generic/generic #dimm 0-0-0 |
| 45 | device i2c 50 on end |
| 46 | end |
| 47 | chip drivers/generic/generic #dimm 0-0-1 |
| 48 | device i2c 51 on end |
| 49 | end |
| 50 | end # SM |
| 51 | device pci 14.1 off end # IDE 0x439c |
| 52 | device pci 14.2 on end # HDA 0x4383 |
| 53 | device pci 14.3 on # LPC 0x439d |
| 54 | chip superio/fintek/f71869ad |
Edward O'Callaghan | dd2e8c3 | 2014-04-24 02:58:11 +1000 | [diff] [blame] | 55 | register "multi_function_register_1" = "0x01" |
| 56 | register "multi_function_register_2" = "0x6f" |
| 57 | register "multi_function_register_3" = "0x24" |
| 58 | register "multi_function_register_4" = "0x00" |
| 59 | register "multi_function_register_5" = "0x60" |
Edward O'Callaghan | 63f28c0 | 2014-04-26 15:21:45 +1000 | [diff] [blame] | 60 | # HWM configuration registers |
| 61 | register "hwm_smbus_address" = "0x98" |
| 62 | register "hwm_smbus_control_reg" = "0x02" |
| 63 | register "hwm_fan_type_sel_reg" = "0x00" |
| 64 | register "hwm_fan1_temp_adj_rate_reg" = "0x33" |
| 65 | register "hwm_fan_mode_sel_reg" = "0x07" |
| 66 | register "hwm_fan1_idx_rpm_mode" = "0x0e" |
| 67 | register "hwm_fan1_seg1_speed_count" = "0xff" |
| 68 | register "hwm_fan1_seg2_speed_count" = "0x0e" |
| 69 | register "hwm_fan1_seg3_speed_count" = "0x07" |
| 70 | register "hwm_fan1_temp_map_sel" = "0x8c" |
| 71 | # |
Edward O'Callaghan | 6e56de3 | 2014-01-25 21:46:10 +1100 | [diff] [blame] | 72 | # XXX: 4e is the default index port and .xy is the |
| 73 | # LDN indexing the pnp_info array found in the superio.c |
| 74 | # NB: Jetway board changes the default (0x4e) index port to (0x2e) by pin 124, |
| 75 | # see page 18 from Fintek F71869 V1.1 datasheet. |
Edward O'Callaghan | bbe3e44 | 2014-05-02 03:11:42 +1000 | [diff] [blame] | 76 | device pnp 2e.00 off # Floppy |
| 77 | io 0x60 = 0x3f0 |
| 78 | irq 0x70 = 6 |
| 79 | drq 0x74 = 2 |
| 80 | end |
| 81 | device pnp 2e.01 on # COM1 |
| 82 | io 0x60 = 0x3f8 |
| 83 | irq 0x70 = 4 |
| 84 | end |
Edward O'Callaghan | 6e56de3 | 2014-01-25 21:46:10 +1100 | [diff] [blame] | 85 | # COM2 not physically wired on board. |
Edward O'Callaghan | bbe3e44 | 2014-05-02 03:11:42 +1000 | [diff] [blame] | 86 | device pnp 2e.02 off # COM2 |
| 87 | io 0x60 = 0x2f8 |
| 88 | irq 0x70 = 3 |
| 89 | end |
| 90 | device pnp 2e.03 off # Parallel Port |
| 91 | io 0x60 = 0x378 |
| 92 | irq 0x70 = 7 |
| 93 | drq 0x74 = 3 |
| 94 | end |
| 95 | device pnp 2e.04 on # Hardware Monitor |
| 96 | io 0x60 = 0x225 # Fintek datasheet says 0x295. |
| 97 | irq 0x70 = 0 |
| 98 | end |
| 99 | device pnp 2e.05 on # KBC |
| 100 | io 0x60 = 0x060 |
| 101 | irq 0x70 = 1 # Keyboard IRQ |
| 102 | irq 0x72 = 12 # Mouse IRQ |
| 103 | end |
| 104 | device pnp 2e.06 off end # GPIO |
Edward O'Callaghan | a7e2cc5 | 2014-05-08 20:45:09 +1000 | [diff] [blame] | 105 | device pnp 2e.07 on end # WDT |
| 106 | device pnp 2e.08 off end # CIR |
Edward O'Callaghan | bbe3e44 | 2014-05-02 03:11:42 +1000 | [diff] [blame] | 107 | device pnp 2e.0a on end # PME |
| 108 | end # f71869ad |
| 109 | end #LPC |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 110 | device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} |
Edward O'Callaghan | 6e56de3 | 2014-01-25 21:46:10 +1100 | [diff] [blame] | 111 | device pci 14.5 on end # OHCI FS/LS USB (0x4399) |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 112 | device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) |
Edward O'Callaghan | 6e56de3 | 2014-01-25 21:46:10 +1100 | [diff] [blame] | 113 | device pci 15.0 on end # PCIe PortA (0x43a0) GbE MAC: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 (10ec:8168) |
Edward O'Callaghan | 93fa422 | 2014-03-04 23:54:16 +1100 | [diff] [blame] | 114 | device pci 15.1 on end # PCIe PortB |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 115 | device pci 15.2 off end # PCIe PortC |
| 116 | device pci 15.3 off end # PCIe PortD |
Edward O'Callaghan | 6e56de3 | 2014-01-25 21:46:10 +1100 | [diff] [blame] | 117 | device pci 16.0 on end # OHCI USB 10-13 (0x4397) |
| 118 | device pci 16.2 on end # EHCI USB 10-13 (0x4396) |
Edward O'Callaghan | 93fa422 | 2014-03-04 23:54:16 +1100 | [diff] [blame] | 119 | register "gpp_configuration" = "4" # GPP_CFGMODE_X1111 - PortA-D on 15.0-3 are each x1 lanes. |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 120 | register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE |
| 121 | |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 122 | end #southbridge/amd/cimx/sb800 |
| 123 | # end # device pci 18.0 |
| 124 | # These seem unnecessary |
| 125 | device pci 18.0 on end |
| 126 | device pci 18.1 on end |
| 127 | device pci 18.2 on end |
| 128 | device pci 18.3 on end |
| 129 | device pci 18.4 on end |
| 130 | device pci 18.5 on end |
| 131 | device pci 18.6 on end |
| 132 | device pci 18.7 on end |
| 133 | |
Edward O'Callaghan | 6e56de3 | 2014-01-25 21:46:10 +1100 | [diff] [blame] | 134 | # |
| 135 | # TODO: Verify the proper SocketId/MemChannelId/DimmId addresses of the SPD |
| 136 | # with i2cdump tool. |
| 137 | # Notes: 0xa0=0x50*2, 0xa2=0x51*2.. 0x50-0x54 are usually RAM modules on the SMBus. |
| 138 | # |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 139 | register "spdAddrLookup" = " |
| 140 | { |
| 141 | { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses |
| 142 | { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses |
| 143 | }" |
| 144 | |
| 145 | end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex |
| 146 | end #domain |
| 147 | end #northbridge/amd/agesa/family14/root_complex |