| # |
| # This file is part of the coreboot project. |
| # |
| # Copyright (C) 2011 Advanced Micro Devices, Inc. |
| # Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>. |
| # |
| # This program is free software; you can redistribute it and/or modify |
| # it under the terms of the GNU General Public License as published by |
| # the Free Software Foundation; version 2 of the License. |
| # |
| # This program is distributed in the hope that it will be useful, |
| # but WITHOUT ANY WARRANTY; without even the implied warranty of |
| # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| # GNU General Public License for more details. |
| # |
| chip northbridge/amd/agesa/family14/root_complex |
| device cpu_cluster 0 on |
| chip cpu/amd/agesa/family14 |
| device lapic 0 on end |
| end |
| end |
| device domain 0 on |
| subsystemid 0x1022 0x1510 inherit |
| chip northbridge/amd/agesa/family14 # CPU side of HT root complex |
| # device pci 18.0 on # northbridge |
| chip northbridge/amd/agesa/family14 # PCI side of HT root complex |
| device pci 0.0 on end # Root Complex |
| device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456] |
| # device pci 1.1 on end # Internal Audio P2P bridge 0x1314 |
| device pci 4.0 on end # PCIE P2P bridge PCIe slot |
| device pci 5.0 off end # PCIE P2P bridge |
| device pci 6.0 on end # GbE MAC: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 (10ec:8168) |
| device pci 7.0 off end # PCIE P2P bridge |
| device pci 8.0 off end # NB/SB Link P2P bridge |
| end # agesa northbridge |
| |
| chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus |
| device pci 11.0 on end # SATA |
| device pci 12.0 on end # OHCI USB 0-4 |
| device pci 12.2 on end # EHCI USB 0-4 |
| device pci 13.0 on end # OHCI USB 5-9 |
| device pci 13.2 on end # EHCI USB 5-9 |
| device pci 14.0 on # SM |
| chip drivers/generic/generic #dimm 0-0-0 |
| device i2c 50 on end |
| end |
| chip drivers/generic/generic #dimm 0-0-1 |
| device i2c 51 on end |
| end |
| end # SM |
| device pci 14.1 off end # IDE 0x439c |
| device pci 14.2 on end # HDA 0x4383 |
| device pci 14.3 on # LPC 0x439d |
| chip superio/fintek/f71869ad |
| register "multi_function_register_1" = "0x01" |
| register "multi_function_register_2" = "0x6f" |
| register "multi_function_register_3" = "0x24" |
| register "multi_function_register_4" = "0x00" |
| register "multi_function_register_5" = "0x60" |
| # HWM configuration registers |
| register "hwm_smbus_address" = "0x98" |
| register "hwm_smbus_control_reg" = "0x02" |
| register "hwm_fan_type_sel_reg" = "0x00" |
| register "hwm_fan1_temp_adj_rate_reg" = "0x33" |
| register "hwm_fan_mode_sel_reg" = "0x07" |
| register "hwm_fan1_idx_rpm_mode" = "0x0e" |
| register "hwm_fan1_seg1_speed_count" = "0xff" |
| register "hwm_fan1_seg2_speed_count" = "0x0e" |
| register "hwm_fan1_seg3_speed_count" = "0x07" |
| register "hwm_fan1_temp_map_sel" = "0x8c" |
| # |
| # XXX: 4e is the default index port and .xy is the |
| # LDN indexing the pnp_info array found in the superio.c |
| # NB: Jetway board changes the default (0x4e) index port to (0x2e) by pin 124, |
| # see page 18 from Fintek F71869 V1.1 datasheet. |
| device pnp 2e.00 off # Floppy |
| io 0x60 = 0x3f0 |
| irq 0x70 = 6 |
| drq 0x74 = 2 |
| end |
| device pnp 2e.01 on # COM1 |
| io 0x60 = 0x3f8 |
| irq 0x70 = 4 |
| end |
| # COM2 not physically wired on board. |
| device pnp 2e.02 off # COM2 |
| io 0x60 = 0x2f8 |
| irq 0x70 = 3 |
| end |
| device pnp 2e.03 off # Parallel Port |
| io 0x60 = 0x378 |
| irq 0x70 = 7 |
| drq 0x74 = 3 |
| end |
| device pnp 2e.04 on # Hardware Monitor |
| io 0x60 = 0x225 # Fintek datasheet says 0x295. |
| irq 0x70 = 0 |
| end |
| device pnp 2e.05 on # KBC |
| io 0x60 = 0x060 |
| irq 0x70 = 1 # Keyboard IRQ |
| irq 0x72 = 12 # Mouse IRQ |
| end |
| device pnp 2e.06 off end # GPIO |
| device pnp 2e.07 on end # WDT |
| device pnp 2e.08 off end # CIR |
| device pnp 2e.0a on end # PME |
| end # f71869ad |
| end #LPC |
| device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} |
| device pci 14.5 on end # OHCI FS/LS USB (0x4399) |
| device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) |
| device pci 15.0 on end # PCIe PortA (0x43a0) GbE MAC: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 (10ec:8168) |
| device pci 15.1 on end # PCIe PortB |
| device pci 15.2 off end # PCIe PortC |
| device pci 15.3 off end # PCIe PortD |
| device pci 16.0 on end # OHCI USB 10-13 (0x4397) |
| device pci 16.2 on end # EHCI USB 10-13 (0x4396) |
| register "gpp_configuration" = "4" # GPP_CFGMODE_X1111 - PortA-D on 15.0-3 are each x1 lanes. |
| register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE |
| |
| end #southbridge/amd/cimx/sb800 |
| # end # device pci 18.0 |
| # These seem unnecessary |
| device pci 18.0 on end |
| device pci 18.1 on end |
| device pci 18.2 on end |
| device pci 18.3 on end |
| device pci 18.4 on end |
| device pci 18.5 on end |
| device pci 18.6 on end |
| device pci 18.7 on end |
| |
| # |
| # TODO: Verify the proper SocketId/MemChannelId/DimmId addresses of the SPD |
| # with i2cdump tool. |
| # Notes: 0xa0=0x50*2, 0xa2=0x51*2.. 0x50-0x54 are usually RAM modules on the SMBus. |
| # |
| register "spdAddrLookup" = " |
| { |
| { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses |
| { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses |
| }" |
| |
| end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex |
| end #domain |
| end #northbridge/amd/agesa/family14/root_complex |