Uwe Hermann | fbd85a1 | 2010-11-07 16:49:31 +0000 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2010 Anders Jenbo <anders@jenbo.dk> |
| 5 | ## |
| 6 | ## This program is free software; you can redistribute it and/or modify |
| 7 | ## it under the terms of the GNU General Public License as published by |
| 8 | ## the Free Software Foundation; either version 2 of the License, or |
| 9 | ## (at your option) any later version. |
| 10 | ## |
| 11 | ## This program is distributed in the hope that it will be useful, |
| 12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | ## GNU General Public License for more details. |
| 15 | ## |
Uwe Hermann | fbd85a1 | 2010-11-07 16:49:31 +0000 | [diff] [blame] | 16 | |
Anders Jenbo | a06f950 | 2010-06-09 08:08:12 +0000 | [diff] [blame] | 17 | chip northbridge/intel/i82810 # Northbridge |
Stefan Reinauer | 0aa37c4 | 2013-02-12 15:20:54 -0800 | [diff] [blame] | 18 | device cpu_cluster 0 on # APIC cluster |
Anders Jenbo | a06f950 | 2010-06-09 08:08:12 +0000 | [diff] [blame] | 19 | chip cpu/intel/socket_PGA370 # CPU |
| 20 | device lapic 0 on end # APIC |
| 21 | end |
| 22 | end |
Stefan Reinauer | 4aff445 | 2013-02-12 14:17:15 -0800 | [diff] [blame] | 23 | device domain 0 on # PCI domain |
Anders Jenbo | a06f950 | 2010-06-09 08:08:12 +0000 | [diff] [blame] | 24 | device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) |
| 25 | device pci 1.0 on end # Chipset Graphics Controller (CGC) |
| 26 | chip southbridge/intel/i82801ax # Southbridge |
| 27 | register "ide0_enable" = "1" |
| 28 | register "ide1_enable" = "1" |
| 29 | |
| 30 | device pci 1e.0 on end # PCI bridge |
| 31 | device pci 1f.0 on # ISA bridge |
| 32 | chip superio/ite/it8712f # Super I/O |
| 33 | device pnp 2e.0 off # Floppy |
| 34 | io 0x60 = 0x3f0 |
| 35 | irq 0x70 = 6 |
| 36 | drq 0x74 = 2 |
| 37 | end |
| 38 | device pnp 2e.1 on # Com1 |
| 39 | io 0x60 = 0x3f8 |
| 40 | irq 0x70 = 4 |
| 41 | end |
| 42 | device pnp 2e.2 on # Com2 |
| 43 | io 0x60 = 0x2f8 |
| 44 | irq 0x70 = 3 |
| 45 | end |
| 46 | device pnp 2e.3 on # Parallel port |
| 47 | io 0x60 = 0x378 |
| 48 | irq 0x70 = 7 |
| 49 | end |
| 50 | device pnp 2e.4 on # EC |
| 51 | io 0x60 = 0x290 |
| 52 | io 0x62 = 0x230 |
| 53 | irq 0x70 = 9 |
| 54 | end |
| 55 | device pnp 2e.5 on # PS/2 keyboard |
| 56 | io 0x60 = 0x60 |
| 57 | io 0x62 = 0x64 |
| 58 | irq 0x70 = 1 |
| 59 | end |
| 60 | device pnp 2e.6 on # PS/2 mouse |
| 61 | irq 0x70 = 12 |
| 62 | end |
| 63 | device pnp 2e.7 on # GPIO |
| 64 | io 0x62 = 0x1220 |
| 65 | io 0x64 = 0x1200 |
| 66 | end |
| 67 | device pnp 2e.8 off # MIDI |
| 68 | io 0x60 = 0x300 |
| 69 | irq 0x70 = 9 |
| 70 | end |
| 71 | device pnp 2e.9 off # Game port |
| 72 | io 0x60 = 0x220 |
| 73 | end |
| 74 | device pnp 2e.a off end # CIR |
| 75 | end |
| 76 | end |
| 77 | device pci 1f.1 on end # IDE |
| 78 | device pci 1f.2 on end # USB |
| 79 | device pci 1f.3 on end # SMBus |
| 80 | end |
| 81 | end |
| 82 | end |