This patch adds the ECS P6IWP-Fe board to coreboot.
Signed-off-by: Anders Jenbo <anders@jenbo.dk>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5623 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
diff --git a/src/mainboard/ecs/p6iwp-fe/devicetree.cb b/src/mainboard/ecs/p6iwp-fe/devicetree.cb
new file mode 100644
index 0000000..18bb8c8
--- /dev/null
+++ b/src/mainboard/ecs/p6iwp-fe/devicetree.cb
@@ -0,0 +1,66 @@
+chip northbridge/intel/i82810 # Northbridge
+ device lapic_cluster 0 on # APIC cluster
+ chip cpu/intel/socket_PGA370 # CPU
+ device lapic 0 on end # APIC
+ end
+ end
+ device pci_domain 0 on # PCI domain
+ device pci 0.0 on end # Graphics Memory Controller Hub (GMCH)
+ device pci 1.0 on end # Chipset Graphics Controller (CGC)
+ chip southbridge/intel/i82801ax # Southbridge
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+
+ device pci 1e.0 on end # PCI bridge
+ device pci 1f.0 on # ISA bridge
+ chip superio/ite/it8712f # Super I/O
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.2 on # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.3 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.4 on # EC
+ io 0x60 = 0x290
+ io 0x62 = 0x230
+ irq 0x70 = 9
+ end
+ device pnp 2e.5 on # PS/2 keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ end
+ device pnp 2e.6 on # PS/2 mouse
+ irq 0x70 = 12
+ end
+ device pnp 2e.7 on # GPIO
+ io 0x62 = 0x1220
+ io 0x64 = 0x1200
+ end
+ device pnp 2e.8 off # MIDI
+ io 0x60 = 0x300
+ irq 0x70 = 9
+ end
+ device pnp 2e.9 off # Game port
+ io 0x60 = 0x220
+ end
+ device pnp 2e.a off end # CIR
+ end
+ end
+ device pci 1f.1 on end # IDE
+ device pci 1f.2 on end # USB
+ device pci 1f.3 on end # SMBus
+ end
+ end
+end