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Sven Schnellee2ca71e2011-02-14 20:02:47 +00001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2009 coresystems GmbH
5 * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of
10 * the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
20 * MA 02110-1301 USA
21 */
22
23#include <console/console.h>
24#include <device/device.h>
25#include <arch/io.h>
26#include <boot/tables.h>
27#include <delay.h>
28#include <arch/coreboot_tables.h>
29#include "chip.h"
30#include <device/pci_def.h>
31#include <device/pci_ops.h>
32#include <arch/io.h>
33#include <ec/lenovo/pmh7/pmh7.h>
34#include <ec/acpi/ec.h>
Sven Schnelleffcd1432011-04-11 19:43:32 +000035#include <ec/lenovo/h8/h8.h>
Sven Schnelle8099cbf2011-04-04 10:57:17 +000036#include <northbridge/intel/i945/i945.h>
Sven Schnelled40d4f772011-06-12 15:08:58 +020037#include <pc80/mc146818rtc.h>
Sven Schnelle50270b82011-04-27 19:48:05 +000038#include "dock.h"
Sven Schnellee2ca71e2011-02-14 20:02:47 +000039
Sven Schnelleb31eb3e2011-04-05 13:00:14 +000040static void mainboard_enable(device_t dev)
41{
Sven Schnelle50270b82011-04-27 19:48:05 +000042 device_t dev0, idedev;
Sven Schnelled40d4f772011-06-12 15:08:58 +020043 u8 defaults_loaded = 0;
Sven Schnelleb31eb3e2011-04-05 13:00:14 +000044
Sven Schnelle8d0b86c2011-07-11 18:36:16 +020045 ec_clr_bit(0x03, 2);
46
47 if (inb(0x164c) & 0x08) {
48 ec_set_bit(0x03, 2);
49 ec_write(0x0c, 0x88);
50 }
Sven Schnelle8099cbf2011-04-04 10:57:17 +000051 /* If we're resuming from suspend, blink suspend LED */
52 dev0 = dev_find_slot(0, PCI_DEVFN(0,0));
Sven Schnelled8c68a92011-06-15 09:26:34 +020053 if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC)
Sven Schnelle8099cbf2011-04-04 10:57:17 +000054 ec_write(0x0c, 0xc7);
Sven Schnelle50270b82011-04-27 19:48:05 +000055
56 idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1));
57 if (idedev && idedev->chip_info && dock_ultrabay_device_present()) {
58 struct southbridge_intel_i82801gx_config *config = idedev->chip_info;
59 config->ide_enable_primary = 1;
60 /* enable Ultrabay power */
61 outb(inb(0x1628) | 0x01, 0x1628);
62 ec_write(0x0c, 0x84);
63 } else {
64 /* disable Ultrabay power */
65 outb(inb(0x1628) & ~0x01, 0x1628);
66 ec_write(0x0c, 0x04);
67 }
Sven Schnelled40d4f772011-06-12 15:08:58 +020068
69 if (get_option(&defaults_loaded, "cmos_defaults_loaded") < 0) {
70 printk(BIOS_INFO, "failed to get cmos_defaults_loaded");
71 defaults_loaded = 0;
72 }
73
74 if (!defaults_loaded) {
75 printk(BIOS_INFO, "Restoring CMOS defaults\n");
76 set_option("tft_brightness", &(u8[]){ 0xff });
77 set_option("volume", &(u8[]){ 0x03 });
78 set_option("cmos_defaults_loaded", &(u8[]){ 0x01 });
79 }
Sven Schnellee2ca71e2011-02-14 20:02:47 +000080}
81
82struct chip_operations mainboard_ops = {
83 CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER)
84 .enable_dev = mainboard_enable,
85};
86