Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <stddef.h> |
| 21 | #include <arch/cpu.h> |
| 22 | #include <arch/io.h> |
| 23 | #include <arch/cbfs.h> |
| 24 | #include <arch/stages.h> |
| 25 | #include <console/console.h> |
| 26 | #include <cbmem.h> |
| 27 | #include <cpu/x86/mtrr.h> |
Aaron Durbin | dc249f6 | 2013-10-10 21:03:50 -0500 | [diff] [blame] | 28 | #include <ramstage_cache.h> |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 29 | #include <romstage_handoff.h> |
Aaron Durbin | 794bddf | 2013-09-27 11:38:36 -0500 | [diff] [blame] | 30 | #include <timestamp.h> |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 31 | #include <baytrail/gpio.h> |
| 32 | #include <baytrail/iomap.h> |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 33 | #include <baytrail/lpc.h> |
| 34 | #include <baytrail/pci_devs.h> |
Aaron Durbin | dc249f6 | 2013-10-10 21:03:50 -0500 | [diff] [blame] | 35 | #include <baytrail/reset.h> |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 36 | #include <baytrail/romstage.h> |
Aaron Durbin | 7837be6 | 2013-10-21 22:32:00 -0500 | [diff] [blame^] | 37 | #include <baytrail/smm.h> |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 38 | |
Aaron Durbin | 794bddf | 2013-09-27 11:38:36 -0500 | [diff] [blame] | 39 | static inline uint64_t timestamp_get(void) |
| 40 | { |
| 41 | return rdtscll(); |
| 42 | } |
| 43 | |
| 44 | static inline tsc_t ts64_to_tsc(uint64_t ts) |
| 45 | { |
| 46 | tsc_t tsc = { |
| 47 | .lo = ts, |
| 48 | .hi = ts >> 32, |
| 49 | }; |
| 50 | return tsc; |
| 51 | } |
| 52 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 53 | /* The cache-as-ram assembly file calls romstage_main() after setting up |
| 54 | * cache-as-ram. romstage_main() will then call the mainboards's |
| 55 | * mainboard_romstage_entry() function. That function then calls |
| 56 | * romstage_common() below. The reason for the back and forth is to provide |
| 57 | * common entry point from cache-as-ram while still allowing for code sharing. |
| 58 | * Because we can't use global variables the stack is used for allocations -- |
| 59 | * thus the need to call back and forth. */ |
| 60 | |
| 61 | static void *setup_stack_and_mttrs(void); |
| 62 | |
| 63 | static void program_base_addresses(void) |
| 64 | { |
| 65 | uint32_t reg; |
| 66 | const uint32_t lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); |
| 67 | |
| 68 | /* Memory Mapped IO registers. */ |
| 69 | reg = PMC_BASE_ADDRESS | 2; |
| 70 | pci_write_config32(lpc_dev, PBASE, reg); |
| 71 | reg = IO_BASE_ADDRESS | 2; |
| 72 | pci_write_config32(lpc_dev, IOBASE, reg); |
| 73 | reg = ILB_BASE_ADDRESS | 2; |
| 74 | pci_write_config32(lpc_dev, IBASE, reg); |
| 75 | reg = SPI_BASE_ADDRESS | 2; |
| 76 | pci_write_config32(lpc_dev, SBASE, reg); |
| 77 | reg = MPHY_BASE_ADDRESS | 2; |
| 78 | pci_write_config32(lpc_dev, MPBASE, reg); |
Aaron Durbin | a64ef62 | 2013-10-03 12:56:37 -0500 | [diff] [blame] | 79 | reg = PUNIT_BASE_ADDRESS | 2; |
| 80 | pci_write_config32(lpc_dev, PUBASE, reg); |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 81 | reg = RCBA_BASE_ADDRESS | 1; |
| 82 | pci_write_config32(lpc_dev, RCBA, reg); |
| 83 | |
| 84 | /* IO Port Registers. */ |
| 85 | reg = ACPI_BASE_ADDRESS | 2; |
| 86 | pci_write_config32(lpc_dev, ABASE, reg); |
| 87 | reg = GPIO_BASE_ADDRESS | 2; |
| 88 | pci_write_config32(lpc_dev, GBASE, reg); |
| 89 | } |
| 90 | |
Aaron Durbin | 794bddf | 2013-09-27 11:38:36 -0500 | [diff] [blame] | 91 | static inline void mark_ts(struct romstage_params *rp, uint64_t ts) |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 92 | { |
Aaron Durbin | 794bddf | 2013-09-27 11:38:36 -0500 | [diff] [blame] | 93 | struct romstage_timestamps *rt = &rp->ts; |
| 94 | |
| 95 | rt->times[rt->count] = ts; |
| 96 | rt->count++; |
| 97 | } |
| 98 | |
| 99 | /* Entry from cache-as-ram.inc. */ |
| 100 | void * asmlinkage romstage_main(unsigned long bist, |
| 101 | uint32_t tsc_low, uint32_t tsc_hi) |
| 102 | { |
| 103 | struct romstage_params rp = { |
| 104 | .bist = bist, |
| 105 | .mrc_params = NULL, |
| 106 | }; |
| 107 | |
| 108 | /* Save initial timestamp from bootblock. */ |
| 109 | mark_ts(&rp, (((uint64_t)tsc_hi) << 32) | (uint64_t)tsc_low); |
| 110 | /* Save romstage begin */ |
| 111 | mark_ts(&rp, timestamp_get()); |
| 112 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 113 | program_base_addresses(); |
| 114 | |
Aaron Durbin | fd039f7 | 2013-10-04 11:11:52 -0500 | [diff] [blame] | 115 | tco_disable(); |
| 116 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 117 | byt_config_com1_and_enable(); |
| 118 | |
| 119 | console_init(); |
| 120 | |
Aaron Durbin | bb3ee83 | 2013-10-07 17:12:20 -0500 | [diff] [blame] | 121 | set_max_freq(); |
| 122 | |
Aaron Durbin | 189aa3e | 2013-10-04 11:17:45 -0500 | [diff] [blame] | 123 | punit_init(); |
| 124 | |
Aaron Durbin | ecf9086 | 2013-09-24 12:36:14 -0500 | [diff] [blame] | 125 | gfx_init(); |
| 126 | |
Aaron Durbin | 5f8ad56 | 2013-10-08 16:54:18 -0500 | [diff] [blame] | 127 | /* Call into mainboard. */ |
| 128 | mainboard_romstage_entry(&rp); |
| 129 | |
| 130 | return setup_stack_and_mttrs(); |
| 131 | } |
| 132 | |
| 133 | /* Entry from the mainboard. */ |
| 134 | void romstage_common(struct romstage_params *params) |
| 135 | { |
| 136 | struct romstage_handoff *handoff; |
| 137 | |
Aaron Durbin | 794bddf | 2013-09-27 11:38:36 -0500 | [diff] [blame] | 138 | mark_ts(params, timestamp_get()); |
| 139 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 140 | /* Initialize RAM */ |
| 141 | raminit(params->mrc_params, 5); |
| 142 | |
Aaron Durbin | 794bddf | 2013-09-27 11:38:36 -0500 | [diff] [blame] | 143 | mark_ts(params, timestamp_get()); |
| 144 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 145 | handoff = romstage_handoff_find_or_add(); |
| 146 | if (handoff != NULL) |
| 147 | handoff->s3_resume = 0; |
| 148 | else |
| 149 | printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); |
| 150 | |
Aaron Durbin | 794bddf | 2013-09-27 11:38:36 -0500 | [diff] [blame] | 151 | /* Save timestamp information. */ |
| 152 | timestamp_init(ts64_to_tsc(params->ts.times[0])); |
| 153 | timestamp_add(TS_START_ROMSTAGE, ts64_to_tsc(params->ts.times[1])); |
| 154 | timestamp_add(TS_BEFORE_INITRAM, ts64_to_tsc(params->ts.times[2])); |
| 155 | timestamp_add(TS_AFTER_INITRAM, ts64_to_tsc(params->ts.times[3])); |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 156 | } |
| 157 | |
| 158 | static void open_up_spi(void) |
| 159 | { |
| 160 | const uintptr_t sbase = SPI_BASE_ADDRESS; |
| 161 | |
| 162 | /* Disable generating SMI when setting WPD bit. */ |
| 163 | write32(sbase + 0xf8, read32(sbase + 0xf8) & ~(1 << 7)); |
| 164 | /* Disable the SMM-only BIOS write and set WPD bit. */ |
| 165 | write32(sbase + 0xfc, 1 | (read32(sbase + 0xfc) & ~(1 << 5))); |
| 166 | } |
| 167 | |
| 168 | void asmlinkage romstage_after_car(void) |
| 169 | { |
| 170 | /* Allow BIOS to program SPI part. */ |
| 171 | open_up_spi(); |
| 172 | |
Aaron Durbin | 794bddf | 2013-09-27 11:38:36 -0500 | [diff] [blame] | 173 | timestamp_add_now(TS_END_ROMSTAGE); |
| 174 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 175 | /* Load the ramstage. */ |
| 176 | copy_and_run(); |
| 177 | while (1); |
| 178 | } |
| 179 | |
| 180 | static inline uint32_t *stack_push(u32 *stack, u32 value) |
| 181 | { |
| 182 | stack = &stack[-1]; |
| 183 | *stack = value; |
| 184 | return stack; |
| 185 | } |
| 186 | |
| 187 | /* Romstage needs quite a bit of stack for decompressing images since the lzma |
| 188 | * lib keeps its state on the stack during romstage. */ |
| 189 | static unsigned long choose_top_of_stack(void) |
| 190 | { |
| 191 | unsigned long stack_top; |
| 192 | const unsigned long romstage_ram_stack_size = 0x5000; |
| 193 | |
| 194 | /* cbmem_add() does a find() before add(). */ |
| 195 | stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, |
| 196 | romstage_ram_stack_size); |
| 197 | stack_top += romstage_ram_stack_size; |
| 198 | return stack_top; |
| 199 | } |
| 200 | |
| 201 | /* setup_stack_and_mttrs() determines the stack to use after |
| 202 | * cache-as-ram is torn down as well as the MTRR settings to use. */ |
| 203 | static void *setup_stack_and_mttrs(void) |
| 204 | { |
| 205 | unsigned long top_of_stack; |
| 206 | int num_mtrrs; |
| 207 | uint32_t *slot; |
| 208 | uint32_t mtrr_mask_upper; |
| 209 | uint32_t top_of_ram; |
| 210 | |
| 211 | /* Top of stack needs to be aligned to a 4-byte boundary. */ |
| 212 | top_of_stack = choose_top_of_stack() & ~3; |
| 213 | slot = (void *)top_of_stack; |
| 214 | num_mtrrs = 0; |
| 215 | |
| 216 | /* The upper bits of the MTRR mask need to set according to the number |
| 217 | * of physical address bits. */ |
| 218 | mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1; |
| 219 | |
| 220 | /* The order for each MTRR is value then base with upper 32-bits of |
| 221 | * each value coming before the lower 32-bits. The reasoning for |
| 222 | * this ordering is to create a stack layout like the following: |
| 223 | * +0: Number of MTRRs |
| 224 | * +4: MTRR base 0 31:0 |
| 225 | * +8: MTRR base 0 63:32 |
| 226 | * +12: MTRR mask 0 31:0 |
| 227 | * +16: MTRR mask 0 63:32 |
| 228 | * +20: MTRR base 1 31:0 |
| 229 | * +24: MTRR base 1 63:32 |
| 230 | * +28: MTRR mask 1 31:0 |
| 231 | * +32: MTRR mask 1 63:32 |
| 232 | */ |
| 233 | |
| 234 | /* Cache the ROM as WP just below 4GiB. */ |
| 235 | slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ |
| 236 | slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRRphysMaskValid); |
| 237 | slot = stack_push(slot, 0); /* upper base */ |
| 238 | slot = stack_push(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT); |
| 239 | num_mtrrs++; |
| 240 | |
| 241 | /* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */ |
| 242 | slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ |
| 243 | slot = stack_push(slot, ~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid); |
| 244 | slot = stack_push(slot, 0); /* upper base */ |
| 245 | slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK); |
| 246 | num_mtrrs++; |
| 247 | |
| 248 | top_of_ram = (uint32_t)cbmem_top(); |
| 249 | /* Cache 8MiB below the top of ram. The top of ram under 4GiB is the |
| 250 | * start of the TSEG region. It is required to be 8MiB aligned. Set |
| 251 | * this area as cacheable so it can be used later for ramstage before |
| 252 | * setting up the entire RAM as cacheable. */ |
| 253 | slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ |
| 254 | slot = stack_push(slot, ~((8 << 20) - 1) | MTRRphysMaskValid); |
| 255 | slot = stack_push(slot, 0); /* upper base */ |
| 256 | slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK); |
| 257 | num_mtrrs++; |
| 258 | |
| 259 | /* Cache 8MiB at the top of ram. Top of ram is where the TSEG |
| 260 | * region resides. However, it is not restricted to SMM mode until |
| 261 | * SMM has been relocated. By setting the region to cacheable it |
| 262 | * provides faster access when relocating the SMM handler as well |
| 263 | * as using the TSEG region for other purposes. */ |
| 264 | slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ |
| 265 | slot = stack_push(slot, ~((8 << 20) - 1) | MTRRphysMaskValid); |
| 266 | slot = stack_push(slot, 0); /* upper base */ |
| 267 | slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK); |
| 268 | num_mtrrs++; |
| 269 | |
| 270 | /* Save the number of MTRRs to setup. Return the stack location |
| 271 | * pointing to the number of MTRRs. */ |
| 272 | slot = stack_push(slot, num_mtrrs); |
| 273 | |
| 274 | return slot; |
| 275 | } |
Aaron Durbin | dc249f6 | 2013-10-10 21:03:50 -0500 | [diff] [blame] | 276 | |
| 277 | struct ramstage_cache *ramstage_cache_location(long *size) |
| 278 | { |
| 279 | char *smm_base; |
| 280 | /* 1MiB cache size */ |
Aaron Durbin | 7837be6 | 2013-10-21 22:32:00 -0500 | [diff] [blame^] | 281 | const long cache_size = CONFIG_SMM_RESERVED_SIZE; |
Aaron Durbin | dc249f6 | 2013-10-10 21:03:50 -0500 | [diff] [blame] | 282 | |
| 283 | /* Ramstage cache lives in TSEG region which is the definition of |
| 284 | * cbmem_top(). */ |
| 285 | smm_base = cbmem_top(); |
| 286 | *size = cache_size; |
Aaron Durbin | 7837be6 | 2013-10-21 22:32:00 -0500 | [diff] [blame^] | 287 | return (void *)&smm_base[smm_region_size() - cache_size]; |
Aaron Durbin | dc249f6 | 2013-10-10 21:03:50 -0500 | [diff] [blame] | 288 | } |
| 289 | |
| 290 | void ramstage_cache_invalid(struct ramstage_cache *cache) |
| 291 | { |
| 292 | #if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE |
| 293 | /* Perform cold reset on invalid ramstage cache. */ |
| 294 | cold_reset(); |
| 295 | #endif |
| 296 | } |
| 297 | |