Matt DeVillier | 57e37c5 | 2020-05-01 12:53:31 -0500 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
Felix Singer | 6c83a71 | 2024-06-23 00:25:18 +0200 | [diff] [blame^] | 3 | device domain 0 on |
| 4 | device ref south_xhci on |
| 5 | register "usb2_ports" = "{ |
| 6 | [0] = USB2_PORT_TYPE_C(OC_SKIP), // Type-C Port |
| 7 | [1] = USB2_PORT_MID(OC0), // Type-A Port (right) |
| 8 | [2] = USB2_PORT_MID(OC_SKIP), // Bluetooth |
| 9 | [3] = USB2_PORT_FLEX(OC_SKIP), // Camera |
| 10 | [5] = USB2_PORT_FLEX(OC2), // Type-A Port (left) |
| 11 | [6] = USB2_PORT_MID(OC_SKIP), // SD |
| 12 | }" |
Matt DeVillier | 57e37c5 | 2020-05-01 12:53:31 -0500 | [diff] [blame] | 13 | |
Felix Singer | 6c83a71 | 2024-06-23 00:25:18 +0200 | [diff] [blame^] | 14 | # OC1 should be for Type-C but it seems to not have been wired, according to |
| 15 | # the available schematics, even though it is labeled as USB_OC_TYPEC. |
| 16 | register "usb3_ports" = "{ |
| 17 | [0] = USB3_PORT_DEFAULT(OC_SKIP), // Type-C Port |
| 18 | [1] = USB3_PORT_DEFAULT(OC0), // Type-A Port (right) |
| 19 | [2] = USB3_PORT_DEFAULT(OC_SKIP), // Type-C Port |
| 20 | }" |
| 21 | end |
| 22 | end |
Matt DeVillier | 57e37c5 | 2020-05-01 12:53:31 -0500 | [diff] [blame] | 23 | end |