skl mainboards/dt: Move usb{2,3}_ports settings into XHCI device scope
Change-Id: I22ba991a9d559b0ecc7b3ceddcfd099890dd6c3a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
diff --git a/src/mainboard/purism/librem_skl/variants/librem13/overridetree.cb b/src/mainboard/purism/librem_skl/variants/librem13/overridetree.cb
index 18ce220..08cf745 100644
--- a/src/mainboard/purism/librem_skl/variants/librem13/overridetree.cb
+++ b/src/mainboard/purism/librem_skl/variants/librem13/overridetree.cb
@@ -1,17 +1,23 @@
chip soc/intel/skylake
- register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port
- register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-A Port (right)
- register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
- register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera
- register "usb2_ports[5]" = "USB2_PORT_FLEX(OC2)" # Type-A Port (left)
- register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # SD
+ device domain 0 on
+ device ref south_xhci on
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_TYPE_C(OC_SKIP), // Type-C Port
+ [1] = USB2_PORT_MID(OC0), // Type-A Port (right)
+ [2] = USB2_PORT_MID(OC_SKIP), // Bluetooth
+ [3] = USB2_PORT_FLEX(OC_SKIP), // Camera
+ [5] = USB2_PORT_FLEX(OC2), // Type-A Port (left)
+ [6] = USB2_PORT_MID(OC_SKIP), // SD
+ }"
- # OC1 should be for Type-C but it seems to not have been wired, according to
- # the available schematics, even though it is labeled as USB_OC_TYPEC.
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port (right)
- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port
-
- device domain 0 on end
+ # OC1 should be for Type-C but it seems to not have been wired, according to
+ # the available schematics, even though it is labeled as USB_OC_TYPEC.
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC_SKIP), // Type-C Port
+ [1] = USB3_PORT_DEFAULT(OC0), // Type-A Port (right)
+ [2] = USB3_PORT_DEFAULT(OC_SKIP), // Type-C Port
+ }"
+ end
+ end
end