Aamir Bohra | 2d689f9 | 2017-05-11 20:27:27 +0530 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2017 Intel Corporation. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <console/console.h> |
| 17 | #include <device/pci.h> |
| 18 | #include <device/pciexp.h> |
| 19 | #include <device/pci_def.h> |
| 20 | #include <device/pci_ids.h> |
| 21 | |
| 22 | #define CACHE_LINE_SIZE 0x10 |
| 23 | /* Latency tolerance reporting, max non-snoop latency value 3.14ms */ |
| 24 | #define PCIE_LTR_MAX_NO_SNOOP_LATENCY_VALUE 0x1003 |
| 25 | /* Latency tolerance reporting, max snoop latency value 3.14ms */ |
| 26 | #define PCIE_LTR_MAX_SNOOP_LATENCY_VALUE 0x1003 |
Subrata Banik | 6bbc91a | 2017-12-07 14:55:51 +0530 | [diff] [blame^] | 27 | /* PCI-E Sub-System ID */ |
| 28 | #define PCIE_SUBSYSTEM_VENDOR_ID 0x94 |
Aamir Bohra | 2d689f9 | 2017-05-11 20:27:27 +0530 | [diff] [blame] | 29 | |
| 30 | static void pch_pcie_init(struct device *dev) |
| 31 | { |
| 32 | u16 reg16; |
| 33 | |
| 34 | printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n"); |
| 35 | |
| 36 | /* Enable SERR */ |
| 37 | pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_SERR); |
| 38 | |
| 39 | /* Enable Bus Master */ |
| 40 | pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_MASTER); |
| 41 | |
| 42 | /* Set Cache Line Size to 0x10 */ |
| 43 | pci_write_config8(dev, PCI_CACHE_LINE_SIZE, CACHE_LINE_SIZE); |
| 44 | |
| 45 | /* disable parity error response, enable ISA */ |
| 46 | pci_update_config16(dev, PCI_BRIDGE_CONTROL, ~1, 1<<2); |
| 47 | |
| 48 | if (IS_ENABLED(CONFIG_PCIE_DEBUG_INFO)) { |
| 49 | printk(BIOS_SPEW, " MBL = 0x%08x\n", |
| 50 | pci_read_config32(dev, PCI_MEMORY_BASE)); |
| 51 | printk(BIOS_SPEW, " PMBL = 0x%08x\n", |
| 52 | pci_read_config32(dev, PCI_PREF_MEMORY_BASE)); |
| 53 | printk(BIOS_SPEW, " PMBU32 = 0x%08x\n", |
| 54 | pci_read_config32(dev, PCI_PREF_BASE_UPPER32)); |
| 55 | printk(BIOS_SPEW, " PMLU32 = 0x%08x\n", |
| 56 | pci_read_config32(dev, PCI_PREF_LIMIT_UPPER32)); |
| 57 | } |
| 58 | |
| 59 | /* Clear errors in status registers */ |
| 60 | reg16 = pci_read_config16(dev, PCI_STATUS); |
| 61 | pci_write_config16(dev, PCI_STATUS, reg16); |
| 62 | reg16 = pci_read_config16(dev, PCI_SEC_STATUS); |
| 63 | pci_write_config16(dev, PCI_SEC_STATUS, reg16); |
| 64 | } |
| 65 | |
| 66 | static void pcie_set_L1_ss_max_latency(device_t dev, unsigned int offset) |
| 67 | { |
| 68 | /* Set max snoop and non-snoop latency for the SOC */ |
| 69 | pci_write_config32(dev, offset, |
| 70 | PCIE_LTR_MAX_NO_SNOOP_LATENCY_VALUE << 16 | |
| 71 | PCIE_LTR_MAX_SNOOP_LATENCY_VALUE); |
| 72 | } |
| 73 | |
Subrata Banik | 6bbc91a | 2017-12-07 14:55:51 +0530 | [diff] [blame^] | 74 | static void pcie_dev_set_subsystem(struct device *dev, |
| 75 | unsigned vendor, unsigned device) |
| 76 | { |
| 77 | pci_write_config32(dev, PCIE_SUBSYSTEM_VENDOR_ID, |
| 78 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 79 | } |
| 80 | |
Aamir Bohra | 2d689f9 | 2017-05-11 20:27:27 +0530 | [diff] [blame] | 81 | static struct pci_operations pcie_ops = { |
| 82 | .set_L1_ss_latency = pcie_set_L1_ss_max_latency, |
Subrata Banik | 6bbc91a | 2017-12-07 14:55:51 +0530 | [diff] [blame^] | 83 | .set_subsystem = pcie_dev_set_subsystem, |
Aamir Bohra | 2d689f9 | 2017-05-11 20:27:27 +0530 | [diff] [blame] | 84 | }; |
| 85 | |
| 86 | static struct device_operations device_ops = { |
| 87 | .read_resources = pci_bus_read_resources, |
| 88 | .set_resources = pci_dev_set_resources, |
| 89 | .enable_resources = pci_bus_enable_resources, |
| 90 | .init = pch_pcie_init, |
| 91 | .scan_bus = pciexp_scan_bridge, |
| 92 | .ops_pci = &pcie_ops, |
| 93 | }; |
| 94 | |
| 95 | static const unsigned short pcie_device_ids[] = { |
| 96 | PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1, |
| 97 | PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP2, |
| 98 | PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP3, |
| 99 | PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP4, |
| 100 | PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP5, |
| 101 | PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP6, |
| 102 | PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP7, |
| 103 | PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP8, |
| 104 | PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP9, |
| 105 | PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP10, |
| 106 | PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP11, |
| 107 | PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP12, |
| 108 | PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP1, |
| 109 | PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP2, |
| 110 | PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP3, |
| 111 | PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP4, |
| 112 | PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP5, |
| 113 | PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP6, |
| 114 | PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP7, |
| 115 | PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP8, |
| 116 | PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP9, |
| 117 | PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP10, |
| 118 | PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP11, |
| 119 | PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP12, |
| 120 | PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP13, |
| 121 | PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP14, |
| 122 | PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP15, |
| 123 | PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP16, |
| 124 | PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP17, |
| 125 | PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP18, |
| 126 | PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP19, |
| 127 | PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP20, |
| 128 | PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP1, |
| 129 | PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP2, |
| 130 | PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP3, |
| 131 | PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP4, |
| 132 | PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP5, |
| 133 | PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP6, |
| 134 | PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP7, |
| 135 | PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP8, |
| 136 | PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP9, |
| 137 | PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP10, |
| 138 | PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP11, |
| 139 | PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP12, |
| 140 | PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP13, |
| 141 | PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP14, |
| 142 | PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP15, |
| 143 | PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP16, |
| 144 | PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP17, |
| 145 | PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP18, |
| 146 | PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP19, |
| 147 | PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP20, |
| 148 | PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP21, |
| 149 | PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP22, |
| 150 | PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP23, |
| 151 | PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP24, |
Lijian Zhao | bbedef9 | 2017-07-29 16:38:38 -0700 | [diff] [blame] | 152 | PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP1, |
| 153 | PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP2, |
| 154 | PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP3, |
| 155 | PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP4, |
| 156 | PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP5, |
| 157 | PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP6, |
| 158 | PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP7, |
| 159 | PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP8, |
| 160 | PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP9, |
| 161 | PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP10, |
| 162 | PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP11, |
| 163 | PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP12, |
| 164 | PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP13, |
| 165 | PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP14, |
| 166 | PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP15, |
| 167 | PCI_DEVICE_ID_INTEL_CNL_LP_PCIE_RP16, |
Aamir Bohra | 2d689f9 | 2017-05-11 20:27:27 +0530 | [diff] [blame] | 168 | 0 |
| 169 | }; |
| 170 | |
| 171 | static const struct pci_driver pch_pcie __pci_driver = { |
| 172 | .ops = &device_ops, |
| 173 | .vendor = PCI_VENDOR_ID_INTEL, |
| 174 | .devices = pcie_device_ids, |
| 175 | }; |