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Tobias Diedrichcee930a2017-02-12 14:09:06 +01001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <stdint.h>
17#include <string.h>
18#include <cbfs.h>
Kyösti Mälkkif1b58b72019-03-01 13:43:02 +020019#include <device/pci_ops.h>
Tobias Diedrichcee930a2017-02-12 14:09:06 +010020#include <console/console.h>
Elyes HAOUAS4ad14462018-06-16 18:29:33 +020021#include <northbridge/intel/sandybridge/sandybridge.h>
22#include <northbridge/intel/sandybridge/raminit_native.h>
23#include <southbridge/intel/bd82x6x/pch.h>
Tobias Diedrichcee930a2017-02-12 14:09:06 +010024#include <southbridge/intel/common/gpio.h>
Tobias Diedrichcee930a2017-02-12 14:09:06 +010025#include "ec.h"
26
27#define SPD_LEN 256
28
Arthur Heymans2b28a162019-11-12 17:21:08 +010029void mainboard_pch_lpc_setup(void)
Tobias Diedrichcee930a2017-02-12 14:09:06 +010030{
Tobias Diedrichcee930a2017-02-12 14:09:06 +010031 /* Memory map KB9012 EC registers */
32 pci_write_config32(
Peter Lemenkov9b7ae2f2018-10-09 13:09:07 +020033 PCH_LPC_DEV, LGMR,
Tobias Diedrichcee930a2017-02-12 14:09:06 +010034 CONFIG_EC_BASE_ADDRESS | 1);
Peter Lemenkov9b7ae2f2018-10-09 13:09:07 +020035 pci_write_config16(PCH_LPC_DEV, BIOS_DEC_EN1, 0xffc0);
Tobias Diedrichcee930a2017-02-12 14:09:06 +010036
Tobias Diedrichcee930a2017-02-12 14:09:06 +010037 /* Enable external USB port power. */
Julius Wernercd49cce2019-03-05 16:53:33 -080038 if (CONFIG(USBDEBUG))
Martin Roth5ef5c002017-03-24 11:08:32 -060039 ec_mm_set_bit(0x3b, 4);
Tobias Diedrichcee930a2017-02-12 14:09:06 +010040}
41
Tobias Diedrichcee930a2017-02-12 14:09:06 +010042const struct southbridge_usb_port mainboard_usb_ports[] = {
43 { 1, 1, 0 },
44 { 1, 0, 0 },
45 { 1, 1, 1 },
46 { 1, 0, 1 },
47 { 1, 1, 2 },
48 { 1, 0, 2 },
49 { 0, 0, 3 },
50 { 0, 1, 3 },
51 { 1, 0, 4 },
52 { 1, 1, 4 },
53 { 1, 1, 5 },
54 { 1, 1, 5 },
55 { 1, 1, 6 },
56 { 1, 1, 6 },
57};
58
Tobias Diedrichcee930a2017-02-12 14:09:06 +010059static const char *mainboard_spd_names[9] = {
60 "ELPIDA 4GB",
61 "SAMSUNG 4GB",
62 "HYNIX 4GB",
63 "ELPIDA 8GB",
64 "SAMSUNG 8GB",
65 "HYNIX 8GB",
66 "ELPIDA 2GB",
67 "SAMSUNG 2GB",
68 "HYNIX 2GB",
69};
70
71void mainboard_get_spd(spd_raw_data *spd, bool id_only)
72{
73 void *spd_file;
74 size_t spd_file_len = 0;
75 const int spd_gpios[] = {71, 70, 16, 48, -1};
76
77 u32 spd_index = get_gpios(spd_gpios);
78 if (spd_index >= ARRAY_SIZE(mainboard_spd_names)) {
79 /* Fallback to pessimistic 2GB image (ELPIDA 2GB) */
80 spd_index = 6;
81 }
82
83 printk(BIOS_INFO, "SPD index %d (%s)\n",
84 spd_index, mainboard_spd_names[spd_index]);
85
86 /* C0S0 is a soldered RAM with no real SPD. Use stored SPD. */
87 spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
88 &spd_file_len);
89
90 if (!spd_file || spd_file_len < SPD_LEN * spd_index + SPD_LEN)
91 die("SPD data not found.");
92
93 memcpy(spd, spd_file + SPD_LEN * spd_index, SPD_LEN);
94}