efdesign98 | ee39ea7 | 2011-06-16 16:39:30 -0700 | [diff] [blame] | 1 | |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * Southbridge Init during POWER-ON |
| 6 | * |
| 7 | * Prepare Southbridge environment during power on stage. |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: CIMx-SB |
| 11 | * @e sub-project: |
| 12 | * @e \$Revision:$ @e \$Date:$ |
| 13 | * |
| 14 | */ |
| 15 | /*;******************************************************************************** |
| 16 | ; |
| 17 | ; Copyright (c) 2011, Advanced Micro Devices, Inc. |
| 18 | ; All rights reserved. |
| 19 | ; |
| 20 | ; Redistribution and use in source and binary forms, with or without |
| 21 | ; modification, are permitted provided that the following conditions are met: |
| 22 | ; * Redistributions of source code must retain the above copyright |
| 23 | ; notice, this list of conditions and the following disclaimer. |
| 24 | ; * Redistributions in binary form must reproduce the above copyright |
| 25 | ; notice, this list of conditions and the following disclaimer in the |
| 26 | ; documentation and/or other materials provided with the distribution. |
| 27 | ; * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 28 | ; its contributors may be used to endorse or promote products derived |
| 29 | ; from this software without specific prior written permission. |
| 30 | ; |
| 31 | ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 32 | ; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 33 | ; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 34 | ; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 35 | ; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 36 | ; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 37 | ; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 38 | ; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 39 | ; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 40 | ; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 41 | ; |
| 42 | ;*********************************************************************************/ |
| 43 | |
| 44 | #include "SbPlatform.h" |
| 45 | #include "cbtypes.h" |
| 46 | #include "AmdSbLib.h" |
| 47 | #include "Hudson-2.h" |
| 48 | |
| 49 | /** |
| 50 | * sbPorInitPciTable - PCI device registers initial during the power on stage. |
| 51 | * |
| 52 | * |
| 53 | * |
| 54 | * |
| 55 | */ |
| 56 | REG8MASK sbPorInitPciTable[] = |
| 57 | { |
| 58 | // SATA device |
| 59 | {0x00, SATA_BUS_DEV_FUN, 0}, |
| 60 | {SB_SATA_REG84 + 3, ~BIT2, 0}, |
| 61 | {SB_SATA_REGA0, ~(BIT2 + BIT3 + BIT4 + BIT5 + BIT6), BIT2 + BIT3 + BIT4 + BIT5}, |
| 62 | {0xFF, 0xFF, 0xFF}, |
| 63 | // LPC Device (Bus 0, Dev 20, Func 3) |
| 64 | {0x00, LPC_BUS_DEV_FUN, 0}, |
| 65 | {SB_LPC_REG44, 0xFF, BIT6 + BIT7}, //Enable COM1 and COM2 |
| 66 | {SB_LPC_REG47, 0xFF, BIT5}, |
| 67 | {SB_LPC_REG48, 0x00, BIT0 + BIT1 + BIT2}, |
| 68 | {SB_LPC_REG7C, 0x00, BIT0 + BIT2}, |
| 69 | {SB_LPC_REG78, 0xF0, BIT2 + BIT3}, // Enable LDRQ pin |
| 70 | {SB_LPC_REGBB, 0xFF, BIT3 + BIT4 + BIT5}, |
| 71 | // A12 set 0xBB [5:3] = 111 to improve SPI timing margin. |
| 72 | // A12 Set 0xBA [6:5] = 11 improve SPI timing margin. (SPI Prefetch enhancement) |
| 73 | {SB_LPC_REGBB, 0xBE, BIT0 + BIT3 + BIT4 + BIT5}, |
| 74 | {SB_LPC_REGBA, 0x9F, BIT5 + BIT6}, |
| 75 | {SB_LPC_REGA4, ~ BIT0, BIT0}, //[BUG Fix] Force EC_PortActive to 1 to fix possible IR non function issue when NO_EC_SUPPORT is defined |
| 76 | {0xFF, 0xFF, 0xFF}, |
| 77 | // P2P Bridge (Bus 0, Dev 20, Func 4) |
| 78 | {0x00, PCIB_BUS_DEV_FUN, 0}, |
| 79 | {SB_PCIB_REG4B, 0xFF, BIT6 + BIT7 + BIT4}, |
| 80 | // ENH230012: Disable P2P bridge decoder for IO address 0x1000-0x1FFF in SBPOR |
| 81 | // ENH260809: Add PCI port 80 support in Hudson-2/3 |
| 82 | #ifdef SB_PCIB_PORT_80_SUPPORT |
| 83 | {SB_PCIB_REG1C, 0x00, 0xF0}, |
| 84 | {SB_PCIB_REG1D, 0x00, 0x00}, |
| 85 | {SB_PCIB_REG04, 0x00, 0x21}, |
| 86 | #endif |
| 87 | {SB_PCIB_REG40, 0xDF, 0x20}, |
| 88 | {SB_PCIB_REG50, 0x02, 0x01}, |
| 89 | {0xFF, 0xFF, 0xFF}, |
| 90 | }; |
| 91 | |
| 92 | /** |
| 93 | * sbPmioPorInitTable - Southbridge ACPI MMIO initial during the power on stage. |
| 94 | * |
| 95 | * |
| 96 | * |
| 97 | * |
| 98 | */ |
| 99 | AcpiRegWrite sbPmioPorInitTable[] = |
| 100 | { |
| 101 | {00, 00, 0xB0, 0xAC}, // Signature |
| 102 | {MISC_BASE >> 8, SB_MISC_REG41, 0x1F, 0x40}, //keep Auxiliary_14Mclk_Sel [12] |
| 103 | //RPR 8.9 USB 3.0 Reference Clock MISC_REG 0x40 [4] = 0 Enable spread-spectrum reference clock. |
| 104 | {MISC_BASE >> 8, SB_MISC_REG40, 0xEF, 0x00}, |
| 105 | // {MISC_BASE >> 8, 0x24 + 2, 0xFF, 0x20}, Testing CPU clk strength |
| 106 | {PMIO_BASE >> 8, SB_PMIOA_REG5D, 0x00, BIT0}, |
| 107 | {PMIO_BASE >> 8, SB_PMIOA_REGD2, 0xCF, BIT4 + BIT5}, |
| 108 | {SMBUS_BASE >> 8, SB_SMBUS_REG12, 0x00, BIT0}, |
| 109 | {PMIO_BASE >> 8, SB_PMIOA_REG28, 0xFF, BIT0 + BIT2}, |
| 110 | {PMIO_BASE >> 8, SB_PMIOA_REG44 + 3, 0x67, BIT7 + BIT3}, // 2.5 Enable Boot Timer |
| 111 | {PMIO_BASE >> 8, SB_PMIOA_REG48, 0xFF, BIT0}, |
| 112 | {PMIO_BASE >> 8, SB_PMIOA_REG00, 0xFF, 0x0E}, |
| 113 | {PMIO_BASE >> 8, SB_PMIOA_REG00 + 2, 0xFF, 0x40}, |
| 114 | {PMIO_BASE >> 8, SB_PMIOA_REG00 + 3, 0xFF, 0x08}, |
| 115 | {PMIO_BASE >> 8, SB_PMIOA_REG34, 0xEF, BIT0 + BIT1}, |
| 116 | {PMIO_BASE >> 8, SB_PMIOA_REGEC, 0xFD, BIT1}, |
| 117 | //{PMIO_BASE >> 8, SB_PMIOA_REG5B, 0xF9, BIT1 + BIT2}, |
| 118 | {PMIO_BASE >> 8, SB_PMIOA_REG08, 0xFE, BIT2 + BIT4}, |
| 119 | {PMIO_BASE >> 8, SB_PMIOA_REG08 + 1, 0xFF, BIT0}, |
| 120 | {PMIO_BASE >> 8, SB_PMIOA_REG54, 0x00, BIT4 + BIT6 + BIT7}, |
| 121 | {PMIO_BASE >> 8, SB_PMIOA_REG04 + 3, 0xFD, BIT1}, |
| 122 | {PMIO_BASE >> 8, SB_PMIOA_REG74, 0xF6, BIT0 + BIT3}, |
| 123 | {PMIO_BASE >> 8, SB_PMIOA_REGF0, ~BIT2, 0x00}, |
| 124 | // RPR GEC I/O Termination Setting |
| 125 | // PM_Reg 0xF6 = Power-on default setting |
| 126 | // PM_Reg 0xF7 = Power-on default setting |
| 127 | // PM_Reg 0xF8 = 0x6C |
| 128 | // PM_Reg 0xF9 = 0x21 |
| 129 | // PM_Reg 0xFA = 0x00 Hudson-2 A12 GEC I/O Pad settings for 3.3V CMOS |
| 130 | {PMIO_BASE >> 8, SB_PMIOA_REGF8, 0x00, 0x6C}, |
| 131 | {PMIO_BASE >> 8, SB_PMIOA_REGF8 + 1, 0x00, 0x07}, |
| 132 | {PMIO_BASE >> 8, SB_PMIOA_REGF8 + 2, 0x00, 0x00}, |
| 133 | // PRP GEC -end |
| 134 | {PMIO_BASE >> 8, SB_PMIOA_REGC4, 0xee, 0x04}, // Release NB_PCIE_RST |
| 135 | {PMIO_BASE >> 8, SB_PMIOA_REGC0 + 2, 0xBF, 0x40}, |
| 136 | |
| 137 | {PMIO_BASE >> 8, SB_PMIOA_REGBE, 0xDF, BIT5}, |
| 138 | |
| 139 | //OBS200280 |
| 140 | //{PMIO_BASE >> 8, SB_PMIOA_REGBE, 0xFF, BIT1}, |
| 141 | |
| 142 | |
| 143 | {0xFF, 0xFF, 0xFF, 0xFF}, |
| 144 | }; |
| 145 | |
| 146 | /** |
| 147 | * sbPowerOnInit - Config Southbridge during power on stage. |
| 148 | * |
| 149 | * |
| 150 | * |
| 151 | * @param[in] pConfig Southbridge configuration structure pointer. |
| 152 | * |
| 153 | */ |
| 154 | VOID |
| 155 | sbPowerOnInit ( |
| 156 | IN AMDSBCFG* pConfig |
| 157 | ) |
| 158 | { |
| 159 | UINT8 dbPortStatus; |
| 160 | //UINT8 dbSysConfig; |
| 161 | UINT32 abValue; |
| 162 | UINT32 abValue2; |
| 163 | UINT8 dbValue; |
| 164 | UINT8 dbEfuse; |
| 165 | UINT32 dbSpiMode; |
| 166 | UINT16 dwAsfPort; |
| 167 | UINT16 smbusBase; |
| 168 | UINT8 cimSataMode; |
| 169 | // UINT8 cimSpiFastReadEnable; |
| 170 | // UINT8 cimSpiFastReadSpeed; |
| 171 | UINT8 cimSataInternal100Spread; |
| 172 | UINT8 indexValue; |
| 173 | UINT32 ddValue; |
| 174 | UINT8 SataPortNum; |
| 175 | UINT8 XhciEfuse; |
| 176 | XhciEfuse = XHCI_EFUSE_LOCATION; |
| 177 | |
| 178 | cimSataMode = pConfig->SATAMODE.SataModeReg; |
| 179 | // if (pConfig->BuildParameters.SpiFastReadEnable != NULL ) { |
| 180 | // cimSpiFastReadEnable = (UINT8) pConfig->BuildParameters.SpiFastReadEnable; |
| 181 | // } else { |
| 182 | // cimSpiFastReadEnable = cimSpiFastReadEnableDefault; |
| 183 | // } |
| 184 | // cimSpiFastReadSpeed = (UINT8) pConfig->BuildParameters.SpiFastReadSpeed; |
| 185 | cimSataInternal100Spread = ( UINT8 ) pConfig->SataInternal100Spread; |
| 186 | |
| 187 | #if SB_CIMx_PARAMETER == 0 |
| 188 | cimSataMode = (UINT8) ((cimSataMode & 0xFB) | cimSataSetMaxGen2Default); |
| 189 | cimSataMode = (UINT8) ((cimSataMode & 0x0F) | cimSataClkModeDefault); |
| 190 | cimSpiFastReadEnable = cimSpiFastReadEnableDefault; |
| 191 | cimSpiFastReadSpeed = cimSpiFastReadSpeedDefault; |
| 192 | cimSataInternal100Spread = SataInternal100SpreadDefault; |
| 193 | #endif |
| 194 | |
| 195 | TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbPowerOnInit \n")); |
| 196 | |
| 197 | // Hudson-2 Only Enabled (Mmio_mem_enablr) // Default value is correct |
| 198 | RWPMIO (SB_PMIOA_REG24, AccWidthUint8, 0xFF, BIT0); |
| 199 | |
| 200 | RWPMIO (0xD3, AccWidthUint8, ~BIT4, 0); |
| 201 | RWPMIO (0xD3, AccWidthUint8, ~BIT4, BIT4); |
| 202 | |
| 203 | if ( pConfig->Cg2Pll == 1 ) { |
| 204 | TurnOffCG2 (); |
| 205 | pConfig->SATAMODE.SataMode.SataClkMode = 0x0a; |
| 206 | } |
| 207 | |
| 208 | //enable CF9 |
| 209 | RWPMIO (0xD2, AccWidthUint8, ~BIT6, 0); |
| 210 | |
| 211 | // Set A-Link bridge access address. This address is set at device 14h, function 0, |
| 212 | // register 0f0h. This is an I/O address. The I/O address must be on 16-byte boundary. |
| 213 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGE0, AccWidthUint32, 00, ALINK_ACCESS_INDEX); |
| 214 | writeAlink (0x80000004, 0x04); // RPR 4.2 Enable Hudson-2 to issue memory read/write requests in the upstream direction |
| 215 | abValue = readAlink (SB_ABCFG_REG9C | (UINT32) (ABCFG << 29)); // RPR 4.5 Disable the credit variable in the downstream arbitration equation |
| 216 | abValue = abValue | BIT0; |
| 217 | writeAlink (SB_ABCFG_REG9C | (UINT32) (ABCFG << 29), abValue); |
| 218 | writeAlink (0x30, 0x10); // AXINDC 0x10[9]=1, Enabling Non-Posted memory write for K8 platform. |
| 219 | writeAlink (0x34, readAlink (0x34) | BIT9); |
| 220 | rwAlink (SB_ABCFG_REG10050 | (UINT32) (ABCFG << 29), ~BIT2, 0x00); |
| 221 | |
| 222 | // Enable external Stickybit register reset feature |
| 223 | //writeAlink (SB_AX_INDXC_REG30 | (UINT32) (AXINDC << 29), 0x30); |
| 224 | //abValue = readAlink (SB_AX_DATAC_REG34 | (UINT32) (AXINDC << 29)); |
| 225 | //abValue |= BIT6 + BIT5; |
| 226 | //writeAlink (SB_AX_DATAC_REG34 | (UINT32) (AXINDC << 29), abValue); |
| 227 | |
| 228 | // Configure UMI target link speed |
| 229 | dbEfuse = PCIE_FORCE_GEN1_EFUSE_LOCATION; |
| 230 | getEfuseStatus (&dbEfuse); |
| 231 | if ( dbEfuse & BIT0 ) { |
| 232 | pConfig->NbSbGen2 = 0; |
| 233 | } |
| 234 | |
| 235 | dbEfuse = FCH_Variant_EFUSE_LOCATION; |
| 236 | getEfuseStatus (&dbEfuse); |
| 237 | if ((dbEfuse == 0x07) || (dbEfuse == 0x08)) { |
| 238 | pConfig->NbSbGen2 = 0; |
| 239 | } |
| 240 | |
| 241 | if (pConfig->NbSbGen2) { |
| 242 | abValue = 2; |
| 243 | abValue2 = BIT0; |
| 244 | } else { |
| 245 | abValue = 1; |
| 246 | abValue2 = 0; |
| 247 | } |
| 248 | rwAlink (SB_AX_INDXP_REGA4, 0xFFFFFFFE, abValue2); |
| 249 | rwAlink ((UINT32)SB_AX_CFG_REG88, 0xFFFFFFF0, abValue); |
| 250 | |
| 251 | if (pConfig->sdbEnable) { |
| 252 | rwAlink (SB_ABCFG_REGC0 | (UINT32) (ABCFG << 29), ~BIT12, 0x00); |
| 253 | RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 0, AccWidthUint8, 0, pConfig->Debug_Reg00); |
| 254 | RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 2, AccWidthUint8, 0, pConfig->Debug_Reg02); |
| 255 | RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 4, AccWidthUint8, 0, pConfig->Debug_Reg04); |
| 256 | RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 1, AccWidthUint8, 0, pConfig->Debug_Reg01); |
| 257 | RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 3, AccWidthUint8, 0, pConfig->Debug_Reg03); |
| 258 | RWMEM (ACPI_MMIO_BASE + SERIAL_DEBUG_BASE + 5, AccWidthUint8, 0, pConfig->Debug_Reg05); |
| 259 | } |
| 260 | |
| 261 | // Set Build option into SB |
| 262 | WritePCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG64, AccWidthUint16 | S3_SAVE, &(pConfig->BuildParameters.SioPmeBaseAddress)); |
| 263 | RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA0, AccWidthUint32 | S3_SAVE, 0x001F, (pConfig->BuildParameters.SpiRomBaseAddress)); |
| 264 | RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG9C, AccWidthUint32 | S3_SAVE, 0, (pConfig->BuildParameters.GecShadowRomBase + 1)); |
| 265 | // Enabled SMBUS0/SMBUS1 (ASF) Base Address |
| 266 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG2C, AccWidthUint16, 06, (pConfig->BuildParameters.Smbus0BaseAddress) + BIT0); //protect BIT[2:1] |
| 267 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG28, AccWidthUint16, 06, (pConfig->BuildParameters.Smbus1BaseAddress) + BIT0); |
| 268 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG60, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPm1EvtBlkAddr)); |
| 269 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG62, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPm1CntBlkAddr)); |
| 270 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG64, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPmTmrBlkAddr)); |
| 271 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG66, AccWidthUint16, 00, (pConfig->BuildParameters.CpuControlBlkAddr)); |
| 272 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG68, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiGpe0BlkAddr)); |
| 273 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6A, AccWidthUint16, 00, (pConfig->BuildParameters.SmiCmdPortAddr)); |
| 274 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6C, AccWidthUint16, 00, (pConfig->BuildParameters.AcpiPmaCntBlkAddr)); |
| 275 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG6E, AccWidthUint16, 00, (pConfig->BuildParameters.SmiCmdPortAddr) + 8); |
| 276 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG48, AccWidthUint32, 00, (pConfig->BuildParameters.WatchDogTimerBase)); |
| 277 | |
| 278 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG2E, AccWidthUint8, ~(BIT1 + BIT2), 0); //clear BIT[2:1] |
| 279 | smbusBase = (UINT16) (pConfig->BuildParameters.Smbus0BaseAddress); |
| 280 | dbValue = 0x00; |
| 281 | WriteIO (smbusBase + 0x14, AccWidthUint8, &dbValue); |
| 282 | |
| 283 | dbEfuse = SATA_FIS_BASE_EFUSE_LOC; |
| 284 | getEfuseStatus (&dbEfuse); |
| 285 | |
| 286 | programSbAcpiMmioTbl ((AcpiRegWrite*) FIXUP_PTR (&sbPmioPorInitTable[0])); |
| 287 | |
| 288 | //RPR 3.4 Enabling ClkRun Function |
| 289 | RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGBB, AccWidthUint8, ~ BIT2, BIT2); |
| 290 | //BUG265683: Mismatch clkrun enable register setting between RPR and CIMX code |
| 291 | RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGD0, AccWidthUint8, ~ BIT2, 0); |
| 292 | |
| 293 | SataPortNum = 0; |
| 294 | for ( SataPortNum = 0; SataPortNum < 0x06; SataPortNum++ ) { |
| 295 | RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, 0xFF, 1 << SataPortNum); |
| 296 | SbStall (2); |
| 297 | RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 2), AccWidthUint8, (0xFF ^ (1 << SataPortNum)) , 0x00); |
| 298 | SbStall (2); |
| 299 | } |
| 300 | |
| 301 | dbValue = 0x0A; |
| 302 | WriteIO (SB_IOMAP_REG70, AccWidthUint8, &dbValue); |
| 303 | ReadIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue); |
| 304 | dbValue &= 0xEF; |
| 305 | WriteIO (SB_IOMAP_REG71, AccWidthUint8, &dbValue); |
| 306 | |
| 307 | RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFFFFFF, (BIT19 + BIT24 + BIT25 + BIT26)); |
| 308 | RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint32 | S3_SAVE, 0xFFC0FFFF, 0 ); |
| 309 | if (pConfig->BuildParameters.SpiSpeed) { |
| 310 | RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint32 | S3_SAVE, ~(BIT13 + BIT12), ((pConfig->BuildParameters.SpiSpeed - 1 ) << 12)); |
| 311 | } |
| 312 | if (pConfig->BuildParameters.SpiFastSpeed) { |
| 313 | RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint32 | S3_SAVE, ~(BIT15 + BIT14), ((pConfig->BuildParameters.SpiFastSpeed - 1 ) << 14)); |
| 314 | } |
| 315 | //if (pConfig->BuildParameters.SpiBurstWrite) { |
| 316 | RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG1C, AccWidthUint32 | S3_SAVE, ~(BIT10), ((pConfig->BuildParameters.SpiBurstWrite) << 10)); |
| 317 | //} |
| 318 | dbSpiMode = pConfig->BuildParameters.SpiMode; |
| 319 | if (pConfig->BuildParameters.SpiMode) { |
| 320 | if ((dbSpiMode == SB_SPI_MODE_QUAL_114) || (dbSpiMode == SB_SPI_MODE_QUAL_112) || (dbSpiMode == SB_SPI_MODE_QUAL_144) || (dbSpiMode == SB_SPI_MODE_QUAL_122)) { |
| 321 | // RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFF0000, 0x013e); |
| 322 | // RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint32 | S3_SAVE, 0xFFFFFF00, 0x80 ); |
| 323 | // RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, 0xFFFEFFFF, 0x10000); |
| 324 | // SbStall (1000); |
| 325 | } |
| 326 | RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG00, AccWidthUint32 | S3_SAVE, ~( BIT18 + BIT29 + BIT30), ((pConfig->BuildParameters.SpiMode & 1) << 18) + ((pConfig->BuildParameters.SpiMode & 6) << 28)); |
| 327 | } |
| 328 | |
| 329 | // if ( cimSpiFastReadSpeed ) { |
| 330 | // RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint16 | S3_SAVE, ~(BIT15 + BIT14), ( cimSpiFastReadSpeed << 14)); |
| 331 | // } |
| 332 | //Program power on pci init table |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame^] | 333 | programPciByteTable ( (REG8MASK*) FIXUP_PTR (&sbPorInitPciTable[0]), |
| 334 | ARRAY_SIZE(sbPorInitPciTable)); |
efdesign98 | ee39ea7 | 2011-06-16 16:39:30 -0700 | [diff] [blame] | 335 | |
| 336 | programSbAcpiMmioTbl ((AcpiRegWrite *) (pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr)); |
| 337 | |
| 338 | RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG6C, AccWidthUint32 | S3_SAVE, 0xFFFFFF00, 0); |
| 339 | |
| 340 | if (pConfig->SATAMODE.SataModeReg == 0) { |
| 341 | pConfig->SATAMODE.SataModeReg = (pConfig->SATAMODE.SataMode.SataController << 0) \ |
| 342 | + (pConfig->SATAMODE.SataMode.SataIdeCombMdPriSecOpt << 1) \ |
| 343 | + (pConfig->SATAMODE.SataMode.SataSetMaxGen2 << 2) \ |
| 344 | + (pConfig->SATAMODE.SataMode.SataIdeCombinedMode << 3) \ |
| 345 | + (pConfig->SATAMODE.SataMode.SataClkMode << 4); |
| 346 | } |
| 347 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0x00, pConfig->SATAMODE.SataModeReg); |
| 348 | |
| 349 | if (dbEfuse & BIT0) { |
| 350 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, 0xFB, 0x04); |
| 351 | } |
| 352 | |
| 353 | ReadMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGDA, AccWidthUint8, &dbPortStatus); |
| 354 | if ( ((dbPortStatus & 0xF0) == 0x10) ) { |
| 355 | RWMEM (ACPI_MMIO_BASE + MISC_BASE + SB_PMIOA_REG08, AccWidthUint8, 0, BIT5); |
| 356 | } |
| 357 | |
| 358 | if ( pConfig->BuildParameters.LegacyFree ) { |
| 359 | RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0x0003C000); |
| 360 | } else { |
| 361 | RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG44), AccWidthUint32 | S3_SAVE, 00, 0xFF03FFD5); |
| 362 | } |
| 363 | |
| 364 | if ( cimSataInternal100Spread ) { |
| 365 | RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x1E, AccWidthUint8, 0xFF, BIT4); |
| 366 | RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG84), AccWidthUint32, 0xFFFFFFFB, 0x00); |
| 367 | } else { |
| 368 | RWMEM (ACPI_MMIO_BASE + MISC_BASE + 0x1E, AccWidthUint8, ~BIT4, 0x00); |
| 369 | } |
| 370 | // Toggle GEVENT4 to reset all GPP devices |
| 371 | sbGppTogglePcieReset (pConfig); |
| 372 | |
| 373 | if ( cimSataInternal100Spread ) { |
| 374 | RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG84), AccWidthUint32, 0xFFFFFFFF, 0x04); |
| 375 | } |
| 376 | |
| 377 | dbValue = 0x08; |
| 378 | WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &dbValue); |
| 379 | ReadIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue); |
| 380 | if ( !pConfig->BuildParameters.EcKbd ) { |
| 381 | // Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input |
| 382 | dbValue = dbValue | 0x0A; |
| 383 | } |
| 384 | WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue); |
| 385 | |
| 386 | dbValue = 0x09; |
| 387 | WriteIO (SB_IOMAP_REGC00, AccWidthUint8, &dbValue); |
| 388 | ReadIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue); |
| 389 | if ( !pConfig->BuildParameters.EcKbd ) { |
| 390 | // Route SIO IRQ1/IRQ12 to USB IRQ1/IRQ12 input |
| 391 | dbValue = dbValue & 0xF9; |
| 392 | } |
| 393 | if ( pConfig->BuildParameters.LegacyFree ) { |
| 394 | // Disable IRQ1/IRQ12 filter enable for Legacy free with USB KBC emulation. |
| 395 | dbValue = dbValue & 0x9F; |
| 396 | } |
| 397 | // Enabled IRQ input |
| 398 | dbValue = dbValue | BIT4; |
| 399 | WriteIO (SB_IOMAP_REGC01, AccWidthUint8, &dbValue); |
| 400 | |
| 401 | dwAsfPort = ((UINT16) pConfig->BuildParameters.Smbus1BaseAddress & 0xFFF0); |
| 402 | if ( dwAsfPort != 0 ) { |
| 403 | RWIO (dwAsfPort + 0x0E, AccWidthUint8, 0x0, 0x70); // 0x70 will change to EQU ( Remote control address) |
| 404 | } |
| 405 | |
| 406 | #ifndef NO_EC_SUPPORT |
| 407 | getChipSysMode (&dbPortStatus); |
| 408 | if ( ((dbPortStatus & ChipSysEcEnable) == 0x00) ) { |
| 409 | // EC is disabled by jumper setting or board config |
| 410 | RWPCI (((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGA4), AccWidthUint16 | S3_SAVE, 0xFFFE, BIT0); |
| 411 | } else { |
| 412 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC4, AccWidthUint8, 0xF7, 0x08); |
| 413 | ecPowerOnInit ( pConfig); |
| 414 | imcSleep ( pConfig); |
| 415 | } |
| 416 | #endif |
| 417 | |
| 418 | |
| 419 | ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x00, AccWidthUint32, &ddValue); |
| 420 | ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x00, AccWidthUint32, &ddValue); |
| 421 | if ( ddValue == 0x78121022 ) { |
| 422 | // |
| 423 | // First Xhci controller. |
| 424 | // |
| 425 | ReadPCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x00, AccWidthUint32, &ddValue); |
| 426 | ddValue = 0; |
| 427 | indexValue = XHCI_REGISTER_BAR03; |
| 428 | WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue); |
| 429 | ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue); |
| 430 | ddValue = (UINT32) dbValue; |
| 431 | |
| 432 | indexValue = XHCI_REGISTER_BAR02; |
| 433 | WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue); |
| 434 | ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue); |
| 435 | ddValue <<= 8; |
| 436 | ddValue |= (UINT32) dbValue; |
| 437 | |
| 438 | indexValue = XHCI_REGISTER_BAR01; |
| 439 | WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue); |
| 440 | ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue); |
| 441 | ddValue <<= 8; |
| 442 | ddValue |= (UINT32) dbValue; |
| 443 | |
| 444 | indexValue = XHCI_REGISTER_BAR00; |
| 445 | WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue); |
| 446 | ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue); |
| 447 | ddValue <<= 8; |
| 448 | ddValue |= (UINT32) dbValue; |
| 449 | WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x10, AccWidthUint32, &ddValue); |
| 450 | |
| 451 | indexValue = XHCI_REGISTER_04H; |
| 452 | WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue); |
| 453 | ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue); |
| 454 | WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x04, AccWidthUint8, &dbValue); |
| 455 | |
| 456 | indexValue = XHCI_REGISTER_0CH; |
| 457 | WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue); |
| 458 | ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue); |
| 459 | WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x0C, AccWidthUint8, &dbValue); |
| 460 | |
| 461 | indexValue = XHCI_REGISTER_3CH; |
| 462 | WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue); |
| 463 | ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue); |
| 464 | WritePCI ((USB_XHCI_BUS_DEV_FUN << 16) + 0x3C, AccWidthUint8, &dbValue); |
| 465 | // |
| 466 | // Second Xhci controller. |
| 467 | // |
| 468 | ReadPCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x00, AccWidthUint32, &ddValue); |
| 469 | ddValue = 0; |
| 470 | indexValue = XHCI1_REGISTER_BAR03; |
| 471 | WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue); |
| 472 | ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue); |
| 473 | ddValue = (UINT32) dbValue; |
| 474 | |
| 475 | indexValue = XHCI1_REGISTER_BAR02; |
| 476 | WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue); |
| 477 | ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue); |
| 478 | ddValue <<= 8; |
| 479 | ddValue |= (UINT32) dbValue; |
| 480 | |
| 481 | indexValue = XHCI1_REGISTER_BAR01; |
| 482 | WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue); |
| 483 | ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue); |
| 484 | ddValue <<= 8; |
| 485 | ddValue |= (UINT32) dbValue; |
| 486 | |
| 487 | indexValue = XHCI1_REGISTER_BAR00; |
| 488 | WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue); |
| 489 | ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue); |
| 490 | ddValue <<= 8; |
| 491 | ddValue |= (UINT32) dbValue; |
| 492 | WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x10, AccWidthUint32, &ddValue); |
| 493 | |
| 494 | indexValue = XHCI1_REGISTER_04H; |
| 495 | WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue); |
| 496 | ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue); |
| 497 | WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x04, AccWidthUint8, &dbValue); |
| 498 | |
| 499 | indexValue = XHCI1_REGISTER_0CH; |
| 500 | WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue); |
| 501 | ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue); |
| 502 | WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x0C, AccWidthUint8, &dbValue); |
| 503 | |
| 504 | indexValue = XHCI1_REGISTER_3CH; |
| 505 | WriteIO (SB_IOMAP_REGCD4, AccWidthUint8, &indexValue); |
| 506 | ReadIO (SB_IOMAP_REGCD5, AccWidthUint8, &dbValue); |
| 507 | WritePCI ((USB_XHCI1_BUS_DEV_FUN << 16) + 0x3C, AccWidthUint8, &dbValue); |
| 508 | } |
| 509 | // RPR 3.2 Enabling SPI ROM Prefetch |
| 510 | // Set LPC cfg 0xBA bit 8 |
| 511 | RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGBA, AccWidthUint16 | S3_SAVE, 0xFFFF, BIT8); |
| 512 | if (IsSbA12Plus ()) { |
| 513 | // Enable SPI Prefetch for USB, set LPC cfg 0xBA bit 7 to 1 for A12 and above |
| 514 | RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGBA, AccWidthUint16 | S3_SAVE, 0xFFFF, BIT7); |
| 515 | } |
| 516 | #ifdef XHCI_SUPPORT |
| 517 | #ifdef XHCI_INIT_IN_ROM_SUPPORT |
| 518 | if ( pConfig->XhciSwitch == 1 ) { |
| 519 | if ( pConfig->S3Resume == 0 ) { |
| 520 | XhciEarlyInit (); |
| 521 | } else { |
| 522 | XhciInitIndirectReg (); |
| 523 | } |
| 524 | } else { |
| 525 | // for power saving. |
| 526 | |
| 527 | // add Efuse checking for Xhci enable/disable |
| 528 | getEfuseStatus (&XhciEfuse); |
| 529 | if ((XhciEfuse & (BIT0 + BIT1)) != (BIT0 + BIT1)) { |
| 530 | RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0xF0FFFBFF, 0x0); |
| 531 | } |
| 532 | } |
| 533 | #endif |
| 534 | #endif |
| 535 | } |
| 536 | |
| 537 | #ifdef XHCI_SUPPORT |
| 538 | VOID |
| 539 | XhciInitIndirectReg ( |
| 540 | ) |
| 541 | { |
| 542 | UINT32 ddDrivingStrength; |
| 543 | UINT32 port; |
| 544 | ddDrivingStrength = 0; |
| 545 | port = 0; |
| 546 | #ifdef SB_USB_BATTERY_CHARGE_SUPPORT |
| 547 | RWXhciIndReg ( 0x40000018, 0xFFFFFFFF, 0x00000030); |
| 548 | #endif |
| 549 | // |
| 550 | // RPR SuperSpeed PHY Configuration (adaptation mode setting) |
| 551 | // |
| 552 | RWXhciIndReg ( SB_XHCI_IND_REG94, 0xFFFFFC00, 0x00000021); |
| 553 | RWXhciIndReg ( SB_XHCI_IND_REGD4, 0xFFFFFC00, 0x00000021); |
| 554 | // |
| 555 | // RPR SuperSpeed PHY Configuration (CR phase and frequency filter settings) |
| 556 | // |
| 557 | RWXhciIndReg ( SB_XHCI_IND_REG98, 0xFFFFFFC0, 0x0000000A); |
| 558 | RWXhciIndReg ( SB_XHCI_IND_REGD8, 0xFFFFFFC0, 0x0000000A); |
| 559 | |
| 560 | // |
| 561 | // RPR BLM Meaasge |
| 562 | // |
| 563 | RWXhciIndReg ( SB_XHCI_IND_REG00, 0xF8FFFFFF, 0x07000000); |
| 564 | // |
| 565 | // RPR 8.13 xHCI USB 2.0 PHY Settings |
| 566 | // Step 1 is done by hardware default |
| 567 | // Step 2 |
| 568 | #ifdef USB3_EHCI_DRIVING_STRENGTH |
| 569 | for (port = 0; port < 4; port ++) { |
| 570 | ddDrivingStrength = (USB3_EHCI_DRIVING_STRENGTH >> (port * 4)) & 0xF; |
| 571 | if (ddDrivingStrength & BIT3) { |
| 572 | ddDrivingStrength &= 0x07; |
| 573 | if (port < 2) { |
| 574 | RWXhci0IndReg ( SB_XHCI_IND60_REG00, 0xFFFE0FF8, (port << 13) + ddDrivingStrength); |
| 575 | RWXhci0IndReg ( SB_XHCI_IND60_REG00, 0xFFFFEFFF, 0x00001000); |
| 576 | } else { |
| 577 | RWXhci1IndReg ( SB_XHCI_IND60_REG00, 0xFFFE0FF8, (port << 13) + ddDrivingStrength); |
| 578 | RWXhci1IndReg ( SB_XHCI_IND60_REG00, 0xFFFFEFFF, 0x00001000); |
| 579 | } |
| 580 | } |
| 581 | } |
| 582 | #endif |
| 583 | |
| 584 | // Step 3 |
| 585 | if (IsSbA11 ()) { |
| 586 | RWXhciIndReg ( SB_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 8)), ((UINT32) (0x00 << 8))); |
| 587 | RWXhciIndReg ( SB_XHCI_IND60_REG08, ~ ((UINT32) (0xff << 8)), ((UINT32) (0x15 << 8))); |
| 588 | } else { |
| 589 | RWXhciIndReg ( SB_XHCI_IND60_REG0C, ~ ((UINT32) (0x0f << 8)), ((UINT32) (0x02 << 8))); |
| 590 | RWXhciIndReg ( SB_XHCI_IND60_REG08, ~ ((UINT32) (0xff << 8)), ((UINT32) (0x0f << 8))); |
| 591 | } |
| 592 | } |
| 593 | |
| 594 | VOID |
| 595 | XhciEarlyInit ( |
| 596 | ) |
| 597 | { |
| 598 | UINT16 BcdAddress; |
| 599 | UINT16 BcdSize; |
| 600 | UINT16 AcdAddress; |
| 601 | UINT16 AcdSize; |
| 602 | UINT16 FwAddress; |
| 603 | UINT16 FwSize; |
| 604 | UINTN XhciFwStarting; |
| 605 | UINT32 SpiValidBase; |
| 606 | UINT32 RegData; |
| 607 | UINT16 i; |
| 608 | |
| 609 | RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0x00000000, 0x00400700); |
| 610 | SbStall (20); |
| 611 | // |
| 612 | // Get ROM SIG starting address for USB firmware starting address (offset 0x0C to SIG address) |
| 613 | // |
| 614 | GetRomSigPtr (&XhciFwStarting); |
| 615 | |
| 616 | if (XhciFwStarting == 0) { |
| 617 | return; |
| 618 | } |
| 619 | |
| 620 | XhciFwStarting = ACPIMMIO32 (XhciFwStarting + FW_TO_SIGADDR_OFFSET); |
| 621 | if (IsLpcRom ()) { |
| 622 | //XHCI firmware re-load |
| 623 | RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGCC, AccWidthUint32 | S3_SAVE, ~BIT2, (BIT2 + BIT1 + BIT0)); |
| 624 | RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REGCC, AccWidthUint32 | S3_SAVE, 0x00000FFF, (UINT32) (XhciFwStarting)); |
| 625 | } |
| 626 | // |
| 627 | // RPR Enable SuperSpeed receive special error case logic. 0x20 bit8 |
| 628 | // RPR Enable USB2.0 RX_Valid Synchronization. 0x20 bit9 |
| 629 | // Enable USB2.0 DIN/SE0 Synchronization. 0x20 bit10 |
| 630 | // |
| 631 | RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG20, AccWidthUint32, 0xFFFFF8FF, 0x00000700); |
| 632 | // |
| 633 | // RPR SuperSpeed PHY Configuration (adaptation timer setting) |
| 634 | // |
| 635 | RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90, AccWidthUint32, 0xFFF00000, 0x000AAAAA); |
| 636 | //RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90 + 0x40, AccWidthUint32, 0xFFF00000, 0x000AAAAA); |
| 637 | |
| 638 | // |
| 639 | // Step 1. to enable Xhci IO and Firmware load mode |
| 640 | // |
| 641 | |
| 642 | #ifdef XHCI_SUPPORT_ONE_CONTROLLER |
| 643 | RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0xF0FFFFFC, 0x00000001); |
| 644 | #else |
| 645 | RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0xF0FFFFFC, 0x00000003); |
| 646 | #endif |
| 647 | RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, 0xEFFFFFFF, 0x10000000); |
| 648 | |
| 649 | // |
| 650 | // Step 2. to read a portion of the USB3_APPLICATION_CODE from BIOS ROM area and program certain registers. |
| 651 | // |
| 652 | |
| 653 | RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA0, AccWidthUint32, 0x00000000, (SPI_HEAD_LENGTH << 16)); |
| 654 | |
| 655 | BcdAddress = ACPIMMIO16 (XhciFwStarting + BCD_ADDR_OFFSET); |
| 656 | BcdSize = ACPIMMIO16 (XhciFwStarting + BCD_SIZE_OFFSET); |
| 657 | RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA4, AccWidthUint16, 0x0000, BcdAddress); |
| 658 | RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA4 + 2, AccWidthUint16, 0x0000, BcdSize); |
| 659 | |
| 660 | AcdAddress = ACPIMMIO16 (XhciFwStarting + ACD_ADDR_OFFSET); |
| 661 | AcdSize = ACPIMMIO16 (XhciFwStarting + ACD_SIZE_OFFSET); |
| 662 | RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA8, AccWidthUint16, 0x0000, AcdAddress); |
| 663 | RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGA8 + 2, AccWidthUint16, 0x0000, AcdSize); |
| 664 | |
| 665 | SpiValidBase = SPI_BASE2 (XhciFwStarting + 4) | SPI_BAR0_VLD | SPI_BASE0 | SPI_BAR1_VLD | SPI_BASE1 | SPI_BAR2_VLD; |
| 666 | RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB0, AccWidthUint32, 0x00000000, SpiValidBase); |
| 667 | |
| 668 | // |
| 669 | // Copy Type0/1/2 data block from ROM image to MMIO starting from 0xC0 |
| 670 | // |
| 671 | for (i = 0; i < SPI_HEAD_LENGTH; i++) { |
| 672 | RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + i, AccWidthUint8, 0, ACPIMMIO8 (XhciFwStarting + i)); |
| 673 | } |
| 674 | |
| 675 | for (i = 0; i < BcdSize; i++) { |
| 676 | RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + SPI_HEAD_LENGTH + i, AccWidthUint8, 0, ACPIMMIO8 (XhciFwStarting + BcdAddress + i)); |
| 677 | } |
| 678 | |
| 679 | for (i = 0; i < AcdSize; i++) { |
| 680 | RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGC0 + SPI_HEAD_LENGTH + BcdSize + i, AccWidthUint8, 0, ACPIMMIO8 (XhciFwStarting + AcdAddress + i)); |
| 681 | } |
| 682 | |
| 683 | // |
| 684 | // Step 3. to enable the instruction RAM preload functionality. |
| 685 | // |
| 686 | FwAddress = ACPIMMIO16 (XhciFwStarting + FW_ADDR_OFFSET); |
| 687 | RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGB4, AccWidthUint16, 0x0000, ACPIMMIO16 (XhciFwStarting + FwAddress)); |
| 688 | FwAddress += 2; |
| 689 | RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG04, AccWidthUint16, 0x0000, FwAddress); |
| 690 | |
| 691 | FwSize = ACPIMMIO16 (XhciFwStarting + FW_SIZE_OFFSET); |
| 692 | RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG04 + 2, AccWidthUint16, 0x0000, FwSize); |
| 693 | |
| 694 | // |
| 695 | // Set the starting address offset for Instruction RAM preload. |
| 696 | // |
| 697 | RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG08, AccWidthUint16, 0x0000, 0); |
| 698 | |
| 699 | RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~BIT29, BIT29); |
| 700 | |
| 701 | for (;;) { |
| 702 | ReadMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00 , AccWidthUint32, &RegData); |
| 703 | if (RegData & BIT30) break; |
| 704 | } |
| 705 | RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~BIT29, 0); |
| 706 | |
| 707 | // |
| 708 | // Step 4. to release resets in XHCI_ACPI_MMIO_AMD_REG00. wait for USPLL to lock by polling USPLL lock. |
| 709 | // |
| 710 | |
| 711 | RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~U3PLL_RESET, 0); //Release U3PLLreset |
| 712 | for (;;) { |
| 713 | ReadMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00 , AccWidthUint32, &RegData); |
| 714 | if (RegData & U3PLL_LOCK) break; |
| 715 | } |
| 716 | |
| 717 | RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~U3PHY_RESET, 0); //Release U3PHY |
| 718 | RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~U3CORE_RESET, 0); //Release core reset |
| 719 | |
| 720 | // RPR 8.8 SuperSpeed PHY Configuration, it is only for A11. |
| 721 | if (IsSbA11 ()) { |
| 722 | RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG90, AccWidthUint32, 0xFFF00000, 0x000AAAAA); // |
| 723 | RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REGD0, AccWidthUint32, 0xFFF00000, 0x000AAAAA); // |
| 724 | } |
| 725 | |
| 726 | XhciInitIndirectReg (); |
| 727 | |
| 728 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, ~(BIT4 + BIT5), 0); // Disable Device 22 |
| 729 | RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEF, AccWidthUint8, ~(BIT7), BIT7); // Enable 2.0 devices |
| 730 | //if (!(pConfig->S4Resume)) { |
| 731 | RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~(BIT21), BIT21); //SMI |
| 732 | //} |
| 733 | // |
| 734 | // Step 5. |
| 735 | // |
| 736 | RWMEM (ACPI_MMIO_BASE + XHCI_BASE + XHCI_ACPI_MMIO_AMD_REG00, AccWidthUint32, ~(BIT17 + BIT18 + BIT19), BIT17 + BIT18); |
| 737 | } |
| 738 | #endif |