commit 6b688f5329e560ef432f6ea281b2fe3d905ef297
author Patrick Georgi <pgeorgi@google.com> Fri Feb 12 13:49:11 2021 +0100
committer Patrick Georgi <pgeorgi@google.com> Mon Feb 15 11:30:40 2021 +0000
tree 831ff654f7477b293421e38b8ed880f2cc740386
parent 036d66be051c4aeeac3b6220974e93645489c27d

src: use ARRAY_SIZE where possible

Generated with a variant of
https://coccinelle.gitlabpages.inria.fr/website/rules/array.cocci

Change-Id: I083704fd48faeb6c67bba3367fbcfe554a9f7c66
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50594
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/vendorcode/amd/cimx/sb900/SBPort.c

diff --git a/src/vendorcode/amd/cimx/sb900/SBPort.c b/src/vendorcode/amd/cimx/sb900/SBPort.c
index 90e878e..75df246 100644
--- a/src/vendorcode/amd/cimx/sb900/SBPort.c
+++ b/src/vendorcode/amd/cimx/sb900/SBPort.c
@@ -330,7 +330,8 @@
 //    RWMEM ((pConfig->BuildParameters.SpiRomBaseAddress) + SB_SPI_MMIO_REG0C, AccWidthUint16 | S3_SAVE, ~(BIT15 + BIT14), ( cimSpiFastReadSpeed << 14));
 //  }
   //Program power on pci init table
-  programPciByteTable ( (REG8MASK*) FIXUP_PTR (&sbPorInitPciTable[0]), sizeof (sbPorInitPciTable) / sizeof (REG8MASK) );
+  programPciByteTable ( (REG8MASK*) FIXUP_PTR (&sbPorInitPciTable[0]),
+                       ARRAY_SIZE(sbPorInitPciTable));
 
   programSbAcpiMmioTbl ((AcpiRegWrite *) (pConfig->OEMPROGTBL.OemProgrammingTablePtr_Ptr));