zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * Graphics Controller family specific service procedure |
| 6 | * |
| 7 | * |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: FCH |
| 12 | * @e \$Revision: 63460 $ @e \$Date: 2011-12-22 19:04:22 -0600 (Thu, 22 Dec 2011) $ |
| 13 | * |
| 14 | */ |
| 15 | |
| 16 | /* |
| 17 | ***************************************************************************** |
| 18 | * |
Siyuan Wang | 641f00c | 2013-06-08 11:50:55 +0800 | [diff] [blame] | 19 | * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. |
| 20 | * All rights reserved. |
| 21 | * |
| 22 | * Redistribution and use in source and binary forms, with or without |
| 23 | * modification, are permitted provided that the following conditions are met: |
| 24 | * * Redistributions of source code must retain the above copyright |
| 25 | * notice, this list of conditions and the following disclaimer. |
| 26 | * * Redistributions in binary form must reproduce the above copyright |
| 27 | * notice, this list of conditions and the following disclaimer in the |
| 28 | * documentation and/or other materials provided with the distribution. |
| 29 | * * Neither the name of Advanced Micro Devices, Inc. nor the names of |
| 30 | * its contributors may be used to endorse or promote products derived |
| 31 | * from this software without specific prior written permission. |
| 32 | * |
| 33 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
| 34 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
| 35 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| 36 | * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY |
| 37 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 38 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
| 39 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
| 40 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 41 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 42 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 43 | * *************************************************************************** |
| 44 | */ |
| 45 | |
| 46 | |
| 47 | /*---------------------------------------------------------------------------------------- |
| 48 | * M O D U L E S U S E D |
| 49 | *---------------------------------------------------------------------------------------- |
| 50 | */ |
| 51 | #include "FchPlatform.h" |
| 52 | #include "Filecode.h" |
| 53 | #define FILECODE PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATAENVSERVICE_FILECODE |
| 54 | |
| 55 | /*---------------------------------------------------------------------------------------- |
| 56 | * D E F I N I T I O N S A N D M A C R O S |
| 57 | *---------------------------------------------------------------------------------------- |
| 58 | */ |
| 59 | // |
| 60 | // Local Routine |
| 61 | // |
| 62 | VOID FchSataCombineControlDataByte (IN UINT8 *ControlReg); |
| 63 | VOID FchSataCombineControlDataWord (IN UINT16 *ControlReg); |
| 64 | |
| 65 | SATA_PHY_SETTING SataPhyTable[] = |
| 66 | { |
| 67 | //Gen3 |
| 68 | {0x0030, 0x0057A607}, |
| 69 | {0x0031, 0x0057A607}, |
| 70 | {0x0032, 0x0057A407}, |
| 71 | {0x0033, 0x0057A407}, |
| 72 | {0x0034, 0x0057A607}, |
| 73 | {0x0035, 0x0057A607}, |
| 74 | {0x0036, 0x0057A403}, |
| 75 | {0x0037, 0x0057A403}, |
| 76 | |
| 77 | //Gen2 |
| 78 | {0x0120, 0x00071302}, |
| 79 | |
| 80 | //Gen1 |
| 81 | {0x0110, 0x00174101} |
| 82 | }; |
| 83 | |
| 84 | /** |
| 85 | * FchInitEnvProgramSataPciRegs - Sata Pci Configuration Space |
| 86 | * register setting |
| 87 | * |
| 88 | * |
| 89 | * @param[in] FchDataPtr Fch configuration structure pointer. |
| 90 | * |
| 91 | */ |
| 92 | VOID |
| 93 | FchInitEnvProgramSataPciRegs ( |
| 94 | IN VOID *FchDataPtr |
| 95 | ) |
| 96 | { |
| 97 | UINT8 *PortRegByte; |
| 98 | UINT16 *PortRegWord; |
| 99 | FCH_DATA_BLOCK *LocalCfgPtr; |
| 100 | AMD_CONFIG_PARAMS *StdHeader; |
| 101 | |
| 102 | LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; |
| 103 | StdHeader = LocalCfgPtr->StdHeader; |
| 104 | // |
| 105 | // Caculate SataPortReg for SATA_ESP_PORT |
| 106 | // |
| 107 | PortRegByte = &(LocalCfgPtr->Sata.SataEspPort.SataPortReg); |
| 108 | FchSataCombineControlDataByte (PortRegByte); |
| 109 | PortRegByte = &(LocalCfgPtr->Sata.SataPortPower.SataPortReg); |
| 110 | FchSataCombineControlDataByte (PortRegByte); |
| 111 | PortRegWord = &(LocalCfgPtr->Sata.SataPortMd.SataPortMode); |
| 112 | FchSataCombineControlDataWord (PortRegWord); |
| 113 | PortRegByte = &(LocalCfgPtr->Sata.SataHotRemovalEnhPort.SataPortReg); |
| 114 | FchSataCombineControlDataByte (PortRegByte); |
| 115 | |
| 116 | // |
| 117 | // Set Sata PCI Configuration Space Write enable |
| 118 | // |
| 119 | SataEnableWriteAccess (StdHeader); |
| 120 | |
| 121 | // |
| 122 | // Enables the SATA watchdog timer register prior to the SATA BIOS post |
| 123 | // |
| 124 | RwPci (((SATA_BUS_DEV_FUN << 16) + 0x44), AccessWidth8, 0xff, BIT0, StdHeader); |
| 125 | |
| 126 | // |
| 127 | // SATA PCI Watchdog timer setting |
| 128 | // Set timer out to 0x20 to fix IDE to SATA Bridge dropping drive issue. |
| 129 | // |
| 130 | RwPci (((SATA_BUS_DEV_FUN << 16) + 0x44 + 2), AccessWidth8, 0, 0x20, StdHeader); |
| 131 | |
| 132 | // |
| 133 | // BIT4:disable fast boot |
| 134 | // |
| 135 | RwPci (((SATA_BUS_DEV_FUN << 16) + 0x040 ), AccessWidth8, 0xff, BIT4, StdHeader); |
| 136 | |
| 137 | // |
| 138 | // Enable IDE DMA read enhancement |
| 139 | // |
| 140 | RwPci (((SATA_BUS_DEV_FUN << 16) + 0x48 + 3), AccessWidth8, 0xff, BIT7, StdHeader); |
| 141 | |
| 142 | // |
| 143 | // Unused SATA Ports Disabled |
| 144 | // |
| 145 | RwPci (((SATA_BUS_DEV_FUN << 16) + 0x040 + 2), AccessWidth8, 0, LocalCfgPtr->Sata.SataPortPower.SataPortReg, StdHeader); |
| 146 | RwPci (((SATA_BUS_DEV_FUN << 16) + 0x48), AccessWidth32, (UINT32) (~ (0x01 << 11)), (UINT32) (0x01 << 11), StdHeader); |
| 147 | RwPci (((SATA_BUS_DEV_FUN << 16) + 0x084 ), AccessWidth32, (UINT32) (~ (0x01 << 31)), (UINT32) (0x00 << 31), StdHeader); |
| 148 | //RPR 9.22 Design Enhancement |
| 149 | RwPci (((SATA_BUS_DEV_FUN << 16) + 0x04C ), AccessWidth32, (UINT32) (~ (0x1 << 18)), (UINT32) (0x1 << 18), StdHeader); |
| 150 | RwPci (((SATA_BUS_DEV_FUN << 16) + 0x04C ), AccessWidth32, (UINT32) (~ (0x1 << 20)), (UINT32) (0x1 << 20), StdHeader); |
| 151 | RwPci (((SATA_BUS_DEV_FUN << 16) + 0x04C ), AccessWidth32, (UINT32) (~ (0x1 << 21)), (UINT32) (0x1 << 21), StdHeader); |
| 152 | RwPci (((SATA_BUS_DEV_FUN << 16) + 0x04C ), AccessWidth32, (UINT32) (~ (0x7 << 26)), (UINT32) (0x7 << 26), StdHeader); |
| 153 | RwPci (((SATA_BUS_DEV_FUN << 16) + 0x04C ), AccessWidth32, (UINT32) (~ (0x3 << 30)), (UINT32) (0x3 << 30), StdHeader); |
| 154 | RwPci (((SATA_BUS_DEV_FUN << 16) + 0x48), AccessWidth32, (UINT32) (~ (0x1 << 30)), (UINT32) (0x1 << 30), StdHeader); |
| 155 | RwPci (((SATA_BUS_DEV_FUN << 16) + 0x04C ), AccessWidth32, (UINT32) (~ (0x1 << 29)), (UINT32) (0x1 << 29), StdHeader); |
| 156 | } |
| 157 | |
| 158 | /** |
| 159 | * FchSataCombineControlDataByte - Combine port control options |
| 160 | * to one control byte. |
| 161 | * |
| 162 | * |
| 163 | * @param[in] *ControlReg - Data pointer for control byte. |
| 164 | * |
| 165 | */ |
| 166 | VOID |
| 167 | FchSataCombineControlDataByte ( |
| 168 | IN UINT8 *ControlReg |
| 169 | ) |
| 170 | { |
| 171 | UINT8 Index; |
| 172 | UINT8 PortControl; |
| 173 | |
| 174 | *ControlReg = 0; |
| 175 | for ( Index = 0; Index < 8; Index++ ) { |
| 176 | PortControl = *( ControlReg + 1 + Index ); |
| 177 | *ControlReg |= PortControl << Index; |
| 178 | } |
| 179 | } |
| 180 | /** |
| 181 | * FchSataCombineControlDataWord - Combine port control options |
| 182 | * to one control Word. |
| 183 | * |
| 184 | * |
| 185 | * @param[in] *ControlReg - Data pointer for control byte. |
| 186 | * |
| 187 | */ |
| 188 | VOID |
| 189 | FchSataCombineControlDataWord ( |
| 190 | IN UINT16 *ControlReg |
| 191 | ) |
| 192 | { |
| 193 | UINT8 Index; |
| 194 | UINT8 PortControl; |
| 195 | |
| 196 | *ControlReg = 0; |
| 197 | for ( Index = 0; Index < 8; Index++ ) { |
| 198 | PortControl = *( (UINT8 *)ControlReg + 2 + Index ); |
| 199 | *ControlReg |= PortControl << (Index * 2); |
| 200 | } |
| 201 | } |
| 202 | |
| 203 | |
| 204 | VOID |
| 205 | FchProgramSataPhy ( |
| 206 | IN AMD_CONFIG_PARAMS *StdHeader |
| 207 | ) |
| 208 | { |
| 209 | SATA_PHY_SETTING *PhyTablePtr; |
| 210 | UINT16 Index; |
| 211 | |
| 212 | PhyTablePtr = &SataPhyTable[0]; |
| 213 | |
Patrick Georgi | 6b688f5 | 2021-02-12 13:49:11 +0100 | [diff] [blame^] | 214 | for (Index = 0; Index < ARRAY_SIZE(SataPhyTable); Index++) { |
zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame] | 215 | RwPci ((SATA_BUS_DEV_FUN << 16) + 0x80, AccessWidth16, 0x00, PhyTablePtr->PhyCoreControlWord, StdHeader); |
| 216 | RwPci ((SATA_BUS_DEV_FUN << 16) + 0x98, AccessWidth32, 0x00, PhyTablePtr->PhyFineTuneDword, StdHeader); |
| 217 | ++PhyTablePtr; |
| 218 | } |
| 219 | |
| 220 | |
| 221 | RwPci ((SATA_BUS_DEV_FUN << 16) + 0x80, AccessWidth16, 0x00, 0x110, StdHeader); |
| 222 | RwPci ((SATA_BUS_DEV_FUN << 16) + 0x09C , AccessWidth32, (UINT32) (~(0x7 << 4)), (UINT32) (0x2 << 4), StdHeader); |
| 223 | RwPci ((SATA_BUS_DEV_FUN << 16) + 0x80, AccessWidth16, 0x00, 0x10, StdHeader); |
| 224 | } |
| 225 | |
| 226 | /** |
| 227 | * FchInitEnvSataRaidProgram - Configuration SATA Raid |
| 228 | * controller |
| 229 | * |
| 230 | * |
| 231 | * |
| 232 | * @param[in] FchDataPtr Fch configuration structure pointer. |
| 233 | * |
| 234 | */ |
| 235 | VOID |
| 236 | FchInitEnvSataRaidProgram ( |
| 237 | IN VOID *FchDataPtr |
| 238 | ) |
| 239 | { |
| 240 | UINT32 SataSSIDValue; |
| 241 | UINT32 DeviceId; |
| 242 | UINT8 EfuseValue; |
| 243 | FCH_DATA_BLOCK *LocalCfgPtr; |
| 244 | AMD_CONFIG_PARAMS *StdHeader; |
| 245 | |
| 246 | LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; |
| 247 | StdHeader = LocalCfgPtr->StdHeader; |
| 248 | |
| 249 | // |
| 250 | // Class code |
| 251 | // |
| 252 | RwPci (((SATA_BUS_DEV_FUN << 16) + 0x08), AccessWidth32, 0, 0x01040040, StdHeader); |
| 253 | // |
| 254 | // Device ID |
| 255 | // |
| 256 | SataSSIDValue = 0; |
| 257 | if (LocalCfgPtr->Sata.SataRaid5Ssid != 0 ) { |
| 258 | SataSSIDValue = LocalCfgPtr->Sata.SataRaid5Ssid; |
| 259 | } |
| 260 | |
| 261 | DeviceId = FCH_SATA_RAID5_DID; |
| 262 | EfuseValue = SATA_EFUSE_LOCATION; |
| 263 | GetEfuseStatus (&EfuseValue, StdHeader); |
| 264 | |
| 265 | if (( EfuseValue & SATA_EFUSE_BIT ) || ( LocalCfgPtr->Sata.SataForceRaid == 1 )) { |
| 266 | DeviceId = FCH_SATA_RAID_DID; |
| 267 | if (LocalCfgPtr->Sata.SataRaidSsid != 0 ) { |
| 268 | SataSSIDValue = LocalCfgPtr->Sata.SataRaidSsid; |
| 269 | } |
| 270 | } |
| 271 | |
| 272 | RwPci (((SATA_BUS_DEV_FUN << 16) + 0x02), AccessWidth16, 0, DeviceId, StdHeader); |
| 273 | // |
| 274 | // SSID |
| 275 | // |
| 276 | if (SataSSIDValue != 0 ) { |
| 277 | RwPci ((SATA_BUS_DEV_FUN << 16) + 0x2C, AccessWidth32, 0, SataSSIDValue, StdHeader); |
| 278 | } |
| 279 | } |
| 280 | |