zbao | 7d94cf9 | 2012-07-02 14:19:14 +0800 | [diff] [blame^] | 1 | /* $NoKeywords:$ */ |
| 2 | /** |
| 3 | * @file |
| 4 | * |
| 5 | * Graphics Controller family specific service procedure |
| 6 | * |
| 7 | * |
| 8 | * |
| 9 | * @xrefitem bom "File Content Label" "Release Content" |
| 10 | * @e project: AGESA |
| 11 | * @e sub-project: FCH |
| 12 | * @e \$Revision: 63460 $ @e \$Date: 2011-12-22 19:04:22 -0600 (Thu, 22 Dec 2011) $ |
| 13 | * |
| 14 | */ |
| 15 | |
| 16 | /* |
| 17 | ***************************************************************************** |
| 18 | * |
| 19 | * Copyright 2008 - 2012 ADVANCED MICRO DEVICES, INC. All Rights Reserved. |
| 20 | * |
| 21 | * AMD is granting you permission to use this software (the Materials) |
| 22 | * pursuant to the terms and conditions of your Software License Agreement |
| 23 | * with AMD. This header does *NOT* give you permission to use the Materials |
| 24 | * or any rights under AMD's intellectual property. Your use of any portion |
| 25 | * of these Materials shall constitute your acceptance of those terms and |
| 26 | * conditions. If you do not agree to the terms and conditions of the Software |
| 27 | * License Agreement, please do not use any portion of these Materials. |
| 28 | * |
| 29 | * CONFIDENTIALITY: The Materials and all other information, identified as |
| 30 | * confidential and provided to you by AMD shall be kept confidential in |
| 31 | * accordance with the terms and conditions of the Software License Agreement. |
| 32 | * |
| 33 | * LIMITATION OF LIABILITY: THE MATERIALS AND ANY OTHER RELATED INFORMATION |
| 34 | * PROVIDED TO YOU BY AMD ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED |
| 35 | * WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO WARRANTIES OF |
| 36 | * MERCHANTABILITY, NONINFRINGEMENT, TITLE, FITNESS FOR ANY PARTICULAR PURPOSE, |
| 37 | * OR WARRANTIES ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. |
| 38 | * IN NO EVENT SHALL AMD OR ITS LICENSORS BE LIABLE FOR ANY DAMAGES WHATSOEVER |
| 39 | * (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS |
| 40 | * INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF AMD'S NEGLIGENCE, |
| 41 | * GROSS NEGLIGENCE, THE USE OF OR INABILITY TO USE THE MATERIALS OR ANY OTHER |
| 42 | * RELATED INFORMATION PROVIDED TO YOU BY AMD, EVEN IF AMD HAS BEEN ADVISED OF |
| 43 | * THE POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS PROHIBIT THE |
| 44 | * EXCLUSION OR LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, |
| 45 | * THE ABOVE LIMITATION MAY NOT APPLY TO YOU. |
| 46 | * |
| 47 | * AMD does not assume any responsibility for any errors which may appear in |
| 48 | * the Materials or any other related information provided to you by AMD, or |
| 49 | * result from use of the Materials or any related information. |
| 50 | * |
| 51 | * You agree that you will not reverse engineer or decompile the Materials. |
| 52 | * |
| 53 | * NO SUPPORT OBLIGATION: AMD is not obligated to furnish, support, or make any |
| 54 | * further information, software, technical information, know-how, or show-how |
| 55 | * available to you. Additionally, AMD retains the right to modify the |
| 56 | * Materials at any time, without notice, and is not obligated to provide such |
| 57 | * modified Materials to you. |
| 58 | * |
| 59 | * U.S. GOVERNMENT RESTRICTED RIGHTS: The Materials are provided with |
| 60 | * "RESTRICTED RIGHTS." Use, duplication, or disclosure by the Government is |
| 61 | * subject to the restrictions as set forth in FAR 52.227-14 and |
| 62 | * DFAR252.227-7013, et seq., or its successor. Use of the Materials by the |
| 63 | * Government constitutes acknowledgement of AMD's proprietary rights in them. |
| 64 | * |
| 65 | * EXPORT ASSURANCE: You agree and certify that neither the Materials, nor any |
| 66 | * direct product thereof will be exported directly or indirectly, into any |
| 67 | * country prohibited by the United States Export Administration Act and the |
| 68 | * regulations thereunder, without the required authorization from the U.S. |
| 69 | * government nor will be used for any purpose prohibited by the same. |
| 70 | * *************************************************************************** |
| 71 | */ |
| 72 | |
| 73 | |
| 74 | /*---------------------------------------------------------------------------------------- |
| 75 | * M O D U L E S U S E D |
| 76 | *---------------------------------------------------------------------------------------- |
| 77 | */ |
| 78 | #include "FchPlatform.h" |
| 79 | #include "Filecode.h" |
| 80 | #define FILECODE PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATAENVSERVICE_FILECODE |
| 81 | |
| 82 | /*---------------------------------------------------------------------------------------- |
| 83 | * D E F I N I T I O N S A N D M A C R O S |
| 84 | *---------------------------------------------------------------------------------------- |
| 85 | */ |
| 86 | // |
| 87 | // Local Routine |
| 88 | // |
| 89 | VOID FchSataCombineControlDataByte (IN UINT8 *ControlReg); |
| 90 | VOID FchSataCombineControlDataWord (IN UINT16 *ControlReg); |
| 91 | |
| 92 | SATA_PHY_SETTING SataPhyTable[] = |
| 93 | { |
| 94 | //Gen3 |
| 95 | {0x0030, 0x0057A607}, |
| 96 | {0x0031, 0x0057A607}, |
| 97 | {0x0032, 0x0057A407}, |
| 98 | {0x0033, 0x0057A407}, |
| 99 | {0x0034, 0x0057A607}, |
| 100 | {0x0035, 0x0057A607}, |
| 101 | {0x0036, 0x0057A403}, |
| 102 | {0x0037, 0x0057A403}, |
| 103 | |
| 104 | //Gen2 |
| 105 | {0x0120, 0x00071302}, |
| 106 | |
| 107 | //Gen1 |
| 108 | {0x0110, 0x00174101} |
| 109 | }; |
| 110 | |
| 111 | /** |
| 112 | * FchInitEnvProgramSataPciRegs - Sata Pci Configuration Space |
| 113 | * register setting |
| 114 | * |
| 115 | * |
| 116 | * @param[in] FchDataPtr Fch configuration structure pointer. |
| 117 | * |
| 118 | */ |
| 119 | VOID |
| 120 | FchInitEnvProgramSataPciRegs ( |
| 121 | IN VOID *FchDataPtr |
| 122 | ) |
| 123 | { |
| 124 | UINT8 *PortRegByte; |
| 125 | UINT16 *PortRegWord; |
| 126 | FCH_DATA_BLOCK *LocalCfgPtr; |
| 127 | AMD_CONFIG_PARAMS *StdHeader; |
| 128 | |
| 129 | LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; |
| 130 | StdHeader = LocalCfgPtr->StdHeader; |
| 131 | // |
| 132 | // Caculate SataPortReg for SATA_ESP_PORT |
| 133 | // |
| 134 | PortRegByte = &(LocalCfgPtr->Sata.SataEspPort.SataPortReg); |
| 135 | FchSataCombineControlDataByte (PortRegByte); |
| 136 | PortRegByte = &(LocalCfgPtr->Sata.SataPortPower.SataPortReg); |
| 137 | FchSataCombineControlDataByte (PortRegByte); |
| 138 | PortRegWord = &(LocalCfgPtr->Sata.SataPortMd.SataPortMode); |
| 139 | FchSataCombineControlDataWord (PortRegWord); |
| 140 | PortRegByte = &(LocalCfgPtr->Sata.SataHotRemovalEnhPort.SataPortReg); |
| 141 | FchSataCombineControlDataByte (PortRegByte); |
| 142 | |
| 143 | // |
| 144 | // Set Sata PCI Configuration Space Write enable |
| 145 | // |
| 146 | SataEnableWriteAccess (StdHeader); |
| 147 | |
| 148 | // |
| 149 | // Enables the SATA watchdog timer register prior to the SATA BIOS post |
| 150 | // |
| 151 | RwPci (((SATA_BUS_DEV_FUN << 16) + 0x44), AccessWidth8, 0xff, BIT0, StdHeader); |
| 152 | |
| 153 | // |
| 154 | // SATA PCI Watchdog timer setting |
| 155 | // Set timer out to 0x20 to fix IDE to SATA Bridge dropping drive issue. |
| 156 | // |
| 157 | RwPci (((SATA_BUS_DEV_FUN << 16) + 0x44 + 2), AccessWidth8, 0, 0x20, StdHeader); |
| 158 | |
| 159 | // |
| 160 | // BIT4:disable fast boot |
| 161 | // |
| 162 | RwPci (((SATA_BUS_DEV_FUN << 16) + 0x040 ), AccessWidth8, 0xff, BIT4, StdHeader); |
| 163 | |
| 164 | // |
| 165 | // Enable IDE DMA read enhancement |
| 166 | // |
| 167 | RwPci (((SATA_BUS_DEV_FUN << 16) + 0x48 + 3), AccessWidth8, 0xff, BIT7, StdHeader); |
| 168 | |
| 169 | // |
| 170 | // Unused SATA Ports Disabled |
| 171 | // |
| 172 | RwPci (((SATA_BUS_DEV_FUN << 16) + 0x040 + 2), AccessWidth8, 0, LocalCfgPtr->Sata.SataPortPower.SataPortReg, StdHeader); |
| 173 | RwPci (((SATA_BUS_DEV_FUN << 16) + 0x48), AccessWidth32, (UINT32) (~ (0x01 << 11)), (UINT32) (0x01 << 11), StdHeader); |
| 174 | RwPci (((SATA_BUS_DEV_FUN << 16) + 0x084 ), AccessWidth32, (UINT32) (~ (0x01 << 31)), (UINT32) (0x00 << 31), StdHeader); |
| 175 | //RPR 9.22 Design Enhancement |
| 176 | RwPci (((SATA_BUS_DEV_FUN << 16) + 0x04C ), AccessWidth32, (UINT32) (~ (0x1 << 18)), (UINT32) (0x1 << 18), StdHeader); |
| 177 | RwPci (((SATA_BUS_DEV_FUN << 16) + 0x04C ), AccessWidth32, (UINT32) (~ (0x1 << 20)), (UINT32) (0x1 << 20), StdHeader); |
| 178 | RwPci (((SATA_BUS_DEV_FUN << 16) + 0x04C ), AccessWidth32, (UINT32) (~ (0x1 << 21)), (UINT32) (0x1 << 21), StdHeader); |
| 179 | RwPci (((SATA_BUS_DEV_FUN << 16) + 0x04C ), AccessWidth32, (UINT32) (~ (0x7 << 26)), (UINT32) (0x7 << 26), StdHeader); |
| 180 | RwPci (((SATA_BUS_DEV_FUN << 16) + 0x04C ), AccessWidth32, (UINT32) (~ (0x3 << 30)), (UINT32) (0x3 << 30), StdHeader); |
| 181 | RwPci (((SATA_BUS_DEV_FUN << 16) + 0x48), AccessWidth32, (UINT32) (~ (0x1 << 30)), (UINT32) (0x1 << 30), StdHeader); |
| 182 | RwPci (((SATA_BUS_DEV_FUN << 16) + 0x04C ), AccessWidth32, (UINT32) (~ (0x1 << 29)), (UINT32) (0x1 << 29), StdHeader); |
| 183 | } |
| 184 | |
| 185 | /** |
| 186 | * FchSataCombineControlDataByte - Combine port control options |
| 187 | * to one control byte. |
| 188 | * |
| 189 | * |
| 190 | * @param[in] *ControlReg - Data pointer for control byte. |
| 191 | * |
| 192 | */ |
| 193 | VOID |
| 194 | FchSataCombineControlDataByte ( |
| 195 | IN UINT8 *ControlReg |
| 196 | ) |
| 197 | { |
| 198 | UINT8 Index; |
| 199 | UINT8 PortControl; |
| 200 | |
| 201 | *ControlReg = 0; |
| 202 | for ( Index = 0; Index < 8; Index++ ) { |
| 203 | PortControl = *( ControlReg + 1 + Index ); |
| 204 | *ControlReg |= PortControl << Index; |
| 205 | } |
| 206 | } |
| 207 | /** |
| 208 | * FchSataCombineControlDataWord - Combine port control options |
| 209 | * to one control Word. |
| 210 | * |
| 211 | * |
| 212 | * @param[in] *ControlReg - Data pointer for control byte. |
| 213 | * |
| 214 | */ |
| 215 | VOID |
| 216 | FchSataCombineControlDataWord ( |
| 217 | IN UINT16 *ControlReg |
| 218 | ) |
| 219 | { |
| 220 | UINT8 Index; |
| 221 | UINT8 PortControl; |
| 222 | |
| 223 | *ControlReg = 0; |
| 224 | for ( Index = 0; Index < 8; Index++ ) { |
| 225 | PortControl = *( (UINT8 *)ControlReg + 2 + Index ); |
| 226 | *ControlReg |= PortControl << (Index * 2); |
| 227 | } |
| 228 | } |
| 229 | |
| 230 | |
| 231 | VOID |
| 232 | FchProgramSataPhy ( |
| 233 | IN AMD_CONFIG_PARAMS *StdHeader |
| 234 | ) |
| 235 | { |
| 236 | SATA_PHY_SETTING *PhyTablePtr; |
| 237 | UINT16 Index; |
| 238 | |
| 239 | PhyTablePtr = &SataPhyTable[0]; |
| 240 | |
| 241 | for (Index = 0; Index < (sizeof (SataPhyTable) / sizeof (SATA_PHY_SETTING)); Index++) { |
| 242 | RwPci ((SATA_BUS_DEV_FUN << 16) + 0x80, AccessWidth16, 0x00, PhyTablePtr->PhyCoreControlWord, StdHeader); |
| 243 | RwPci ((SATA_BUS_DEV_FUN << 16) + 0x98, AccessWidth32, 0x00, PhyTablePtr->PhyFineTuneDword, StdHeader); |
| 244 | ++PhyTablePtr; |
| 245 | } |
| 246 | |
| 247 | |
| 248 | RwPci ((SATA_BUS_DEV_FUN << 16) + 0x80, AccessWidth16, 0x00, 0x110, StdHeader); |
| 249 | RwPci ((SATA_BUS_DEV_FUN << 16) + 0x09C , AccessWidth32, (UINT32) (~(0x7 << 4)), (UINT32) (0x2 << 4), StdHeader); |
| 250 | RwPci ((SATA_BUS_DEV_FUN << 16) + 0x80, AccessWidth16, 0x00, 0x10, StdHeader); |
| 251 | } |
| 252 | |
| 253 | /** |
| 254 | * FchInitEnvSataRaidProgram - Configuration SATA Raid |
| 255 | * controller |
| 256 | * |
| 257 | * |
| 258 | * |
| 259 | * @param[in] FchDataPtr Fch configuration structure pointer. |
| 260 | * |
| 261 | */ |
| 262 | VOID |
| 263 | FchInitEnvSataRaidProgram ( |
| 264 | IN VOID *FchDataPtr |
| 265 | ) |
| 266 | { |
| 267 | UINT32 SataSSIDValue; |
| 268 | UINT32 DeviceId; |
| 269 | UINT8 EfuseValue; |
| 270 | FCH_DATA_BLOCK *LocalCfgPtr; |
| 271 | AMD_CONFIG_PARAMS *StdHeader; |
| 272 | |
| 273 | LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; |
| 274 | StdHeader = LocalCfgPtr->StdHeader; |
| 275 | |
| 276 | // |
| 277 | // Class code |
| 278 | // |
| 279 | RwPci (((SATA_BUS_DEV_FUN << 16) + 0x08), AccessWidth32, 0, 0x01040040, StdHeader); |
| 280 | // |
| 281 | // Device ID |
| 282 | // |
| 283 | SataSSIDValue = 0; |
| 284 | if (LocalCfgPtr->Sata.SataRaid5Ssid != 0 ) { |
| 285 | SataSSIDValue = LocalCfgPtr->Sata.SataRaid5Ssid; |
| 286 | } |
| 287 | |
| 288 | DeviceId = FCH_SATA_RAID5_DID; |
| 289 | EfuseValue = SATA_EFUSE_LOCATION; |
| 290 | GetEfuseStatus (&EfuseValue, StdHeader); |
| 291 | |
| 292 | if (( EfuseValue & SATA_EFUSE_BIT ) || ( LocalCfgPtr->Sata.SataForceRaid == 1 )) { |
| 293 | DeviceId = FCH_SATA_RAID_DID; |
| 294 | if (LocalCfgPtr->Sata.SataRaidSsid != 0 ) { |
| 295 | SataSSIDValue = LocalCfgPtr->Sata.SataRaidSsid; |
| 296 | } |
| 297 | } |
| 298 | |
| 299 | RwPci (((SATA_BUS_DEV_FUN << 16) + 0x02), AccessWidth16, 0, DeviceId, StdHeader); |
| 300 | // |
| 301 | // SSID |
| 302 | // |
| 303 | if (SataSSIDValue != 0 ) { |
| 304 | RwPci ((SATA_BUS_DEV_FUN << 16) + 0x2C, AccessWidth32, 0, SataSSIDValue, StdHeader); |
| 305 | } |
| 306 | } |
| 307 | |