Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 2 | |
| 3 | #ifndef HUDSON_H |
| 4 | #define HUDSON_H |
| 5 | |
Marshall Dawson | d8019a6 | 2017-01-29 17:22:36 -0700 | [diff] [blame] | 6 | #include <types.h> |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 7 | #include <device/device.h> |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 8 | |
Marc Jones | d771786 | 2017-04-09 17:55:56 -0600 | [diff] [blame] | 9 | /* Offsets from ACPI_MMIO_BASE |
| 10 | * This is defined by AGESA, but we don't include AGESA headers to avoid |
| 11 | * polluting the namespace. |
| 12 | */ |
Marshall Dawson | c1f3233 | 2017-04-21 13:54:08 -0600 | [diff] [blame] | 13 | #define PM_MMIO_BASE 0xfed80300 |
Marc Jones | d771786 | 2017-04-09 17:55:56 -0600 | [diff] [blame] | 14 | |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 15 | /* Power management index/data registers */ |
Marshall Dawson | c1f3233 | 2017-04-21 13:54:08 -0600 | [diff] [blame] | 16 | #define BIOSRAM_INDEX 0xcd4 |
| 17 | #define BIOSRAM_DATA 0xcd5 |
| 18 | #define PM_INDEX 0xcd6 |
| 19 | #define PM_DATA 0xcd7 |
| 20 | #define PM2_INDEX 0xcd0 |
| 21 | #define PM2_DATA 0xcd1 |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 22 | |
Marshall Dawson | c1f3233 | 2017-04-21 13:54:08 -0600 | [diff] [blame] | 23 | #define PM_ACPI_MMIO_EN 0x24 |
| 24 | #define PM_SERIRQ_CONF 0x54 |
| 25 | #define PM_EVT_BLK 0x60 |
| 26 | #define PM1_CNT_BLK 0x62 |
| 27 | #define PM_TMR_BLK 0x64 |
| 28 | #define PM_CPU_CTRL 0x66 |
| 29 | #define PM_GPE0_BLK 0x68 |
| 30 | #define PM_ACPI_SMI_CMD 0x6A |
| 31 | #define PM_ACPI_CONF 0x74 |
| 32 | #define PM_PMIO_DEBUG 0xD2 |
| 33 | #define PM_MANUAL_RESET 0xD3 |
| 34 | #define PM_HUD_SD_FLASH_CTRL 0xE7 |
| 35 | #define PM_YANG_SD_FLASH_CTRL 0xE8 |
| 36 | #define PM_PCIB_CFG 0xEA |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 37 | |
Marc Jones | 7f2c29b | 2017-04-26 21:55:03 -0600 | [diff] [blame] | 38 | #define HUDSON_ACPI_IO_BASE CONFIG_HUDSON_ACPI_IO_BASE |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 39 | #define ACPI_PM_EVT_BLK (HUDSON_ACPI_IO_BASE + 0x00) /* 4 bytes */ |
| 40 | #define ACPI_PM1_CNT_BLK (HUDSON_ACPI_IO_BASE + 0x04) /* 2 bytes */ |
| 41 | #define ACPI_PM_TMR_BLK (HUDSON_ACPI_IO_BASE + 0x18) /* 4 bytes */ |
| 42 | #define ACPI_GPE0_BLK (HUDSON_ACPI_IO_BASE + 0x10) /* 8 bytes */ |
| 43 | #define ACPI_CPU_CONTROL (HUDSON_ACPI_IO_BASE + 0x08) /* 6 bytes */ |
| 44 | |
Kyösti Mälkki | e742b68 | 2023-04-10 17:03:32 +0300 | [diff] [blame] | 45 | #define ACPI_SCI_IRQ 9 |
| 46 | |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 47 | #define ACPI_SMI_CTL_PORT 0xb2 |
| 48 | #define ACPI_SMI_CMD_CST_CONTROL 0xde |
| 49 | #define ACPI_SMI_CMD_PST_CONTROL 0xad |
| 50 | #define ACPI_SMI_CMD_DISABLE 0xbe |
| 51 | #define ACPI_SMI_CMD_ENABLE 0xef |
| 52 | #define ACPI_SMI_CMD_S4_REQ 0xc0 |
| 53 | |
Marshall Dawson | c1f3233 | 2017-04-21 13:54:08 -0600 | [diff] [blame] | 54 | #define REV_HUDSON_A11 0x11 |
| 55 | #define REV_HUDSON_A12 0x12 |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 56 | |
Marshall Dawson | c1f3233 | 2017-04-21 13:54:08 -0600 | [diff] [blame] | 57 | #define SPIROM_BASE_ADDRESS_REGISTER 0xA0 |
Marc Jones | 6fcaaef | 2017-04-20 16:48:42 -0600 | [diff] [blame] | 58 | #define ROUTE_TPM_2_SPI BIT(3) |
Marshall Dawson | c1f3233 | 2017-04-21 13:54:08 -0600 | [diff] [blame] | 59 | #define SPI_ROM_ENABLE 0x02 |
| 60 | #define SPI_BASE_ADDRESS 0xFEC10000 |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 61 | |
Marshall Dawson | c1f3233 | 2017-04-21 13:54:08 -0600 | [diff] [blame] | 62 | #define LPC_IO_PORT_DECODE_ENABLE 0x44 |
| 63 | #define DECODE_ENABLE_PARALLEL_PORT0 BIT(0) |
| 64 | #define DECODE_ENABLE_PARALLEL_PORT1 BIT(1) |
| 65 | #define DECODE_ENABLE_PARALLEL_PORT2 BIT(2) |
| 66 | #define DECODE_ENABLE_PARALLEL_PORT3 BIT(3) |
| 67 | #define DECODE_ENABLE_PARALLEL_PORT4 BIT(4) |
| 68 | #define DECODE_ENABLE_PARALLEL_PORT5 BIT(5) |
| 69 | #define DECODE_ENABLE_SERIAL_PORT0 BIT(6) |
| 70 | #define DECODE_ENABLE_SERIAL_PORT1 BIT(7) |
| 71 | #define DECODE_ENABLE_SERIAL_PORT2 BIT(8) |
| 72 | #define DECODE_ENABLE_SERIAL_PORT3 BIT(9) |
| 73 | #define DECODE_ENABLE_SERIAL_PORT4 BIT(10) |
| 74 | #define DECODE_ENABLE_SERIAL_PORT5 BIT(11) |
| 75 | #define DECODE_ENABLE_SERIAL_PORT6 BIT(12) |
| 76 | #define DECODE_ENABLE_SERIAL_PORT7 BIT(13) |
| 77 | #define DECODE_ENABLE_AUDIO_PORT0 BIT(14) |
| 78 | #define DECODE_ENABLE_AUDIO_PORT1 BIT(15) |
| 79 | #define DECODE_ENABLE_AUDIO_PORT2 BIT(16) |
| 80 | #define DECODE_ENABLE_AUDIO_PORT3 BIT(17) |
| 81 | #define DECODE_ENABLE_MIDI_PORT0 BIT(18) |
| 82 | #define DECODE_ENABLE_MIDI_PORT1 BIT(19) |
| 83 | #define DECODE_ENABLE_MIDI_PORT2 BIT(20) |
| 84 | #define DECODE_ENABLE_MIDI_PORT3 BIT(21) |
| 85 | #define DECODE_ENABLE_MSS_PORT0 BIT(22) |
| 86 | #define DECODE_ENABLE_MSS_PORT1 BIT(23) |
| 87 | #define DECODE_ENABLE_MSS_PORT2 BIT(24) |
| 88 | #define DECODE_ENABLE_MSS_PORT3 BIT(25) |
| 89 | #define DECODE_ENABLE_FDC_PORT0 BIT(26) |
| 90 | #define DECODE_ENABLE_FDC_PORT1 BIT(27) |
| 91 | #define DECODE_ENABLE_GAME_PORT BIT(28) |
| 92 | #define DECODE_ENABLE_KBC_PORT BIT(29) |
| 93 | #define DECODE_ENABLE_ACPIUC_PORT BIT(30) |
| 94 | #define DECODE_ENABLE_ADLIB_PORT BIT(31) |
Dave Frodin | f364fc7 | 2015-03-13 08:22:17 -0600 | [diff] [blame] | 95 | |
Marc Jones | f962aa5 | 2017-03-22 18:47:49 +0800 | [diff] [blame] | 96 | #define LPC_IO_OR_MEM_DECODE_ENABLE 0x48 |
Marshall Dawson | c1f3233 | 2017-04-21 13:54:08 -0600 | [diff] [blame] | 97 | #define LPC_WIDEIO2_ENABLE BIT(25) |
| 98 | #define LPC_WIDEIO1_ENABLE BIT(24) |
| 99 | #define LPC_WIDEIO0_ENABLE BIT(2) |
Marc Jones | f962aa5 | 2017-03-22 18:47:49 +0800 | [diff] [blame] | 100 | |
| 101 | #define LPC_WIDEIO_GENERIC_PORT 0x64 |
| 102 | |
| 103 | #define LPC_ALT_WIDEIO_RANGE_ENABLE 0x74 |
| 104 | #define LPC_ALT_WIDEIO2_ENABLE BIT(3) |
| 105 | #define LPC_ALT_WIDEIO1_ENABLE BIT(2) |
| 106 | #define LPC_ALT_WIDEIO0_ENABLE BIT(0) |
| 107 | |
Michał Żygowski | 8cee45c | 2019-11-23 18:03:46 +0100 | [diff] [blame] | 108 | #define LPC_TRUSTED_PLATFORM_MODULE 0x7c |
| 109 | #define TPM_12_EN BIT(0) |
| 110 | #define TPM_LEGACY_EN BIT(2) |
| 111 | |
Marc Jones | f962aa5 | 2017-03-22 18:47:49 +0800 | [diff] [blame] | 112 | #define LPC_WIDEIO2_GENERIC_PORT 0x90 |
| 113 | |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 114 | #define SPI_CNTRL0 0x00 |
Marshall Dawson | c1f3233 | 2017-04-21 13:54:08 -0600 | [diff] [blame] | 115 | #define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18)) |
Marshall Dawson | 7b0b9f0 | 2017-01-29 17:29:46 -0700 | [diff] [blame] | 116 | /* Nominal is 16.7MHz on older devices, 33MHz on newer */ |
Marshall Dawson | c1f3233 | 2017-04-21 13:54:08 -0600 | [diff] [blame] | 117 | #define SPI_READ_MODE_NOM 0x00000000 |
| 118 | #define SPI_READ_MODE_DUAL112 ( BIT(29) ) |
| 119 | #define SPI_READ_MODE_QUAD114 ( BIT(29) | BIT(18)) |
| 120 | #define SPI_READ_MODE_DUAL122 (BIT(30) ) |
| 121 | #define SPI_READ_MODE_QUAD144 (BIT(30) | BIT(18)) |
| 122 | #define SPI_READ_MODE_NORMAL66 (BIT(30) | BIT(29) ) |
Marshall Dawson | 7b0b9f0 | 2017-01-29 17:29:46 -0700 | [diff] [blame] | 123 | /* Nominal and SPI_READ_MODE_FAST_HUDSON1 are the only valid choices for H1 */ |
Marshall Dawson | c1f3233 | 2017-04-21 13:54:08 -0600 | [diff] [blame] | 124 | #define SPI_READ_MODE_FAST_HUDSON1 ( BIT(18)) |
| 125 | #define SPI_READ_MODE_FAST (BIT(30) | BIT(29) | BIT(18)) |
| 126 | #define SPI_ARB_ENABLE BIT(19) |
Marshall Dawson | 7b0b9f0 | 2017-01-29 17:29:46 -0700 | [diff] [blame] | 127 | |
Marshall Dawson | c1f3233 | 2017-04-21 13:54:08 -0600 | [diff] [blame] | 128 | #define SPI_CNTRL1 0x0c |
Marshall Dawson | 7b0b9f0 | 2017-01-29 17:29:46 -0700 | [diff] [blame] | 129 | /* Use SPI_SPEED_16M-SPI_SPEED_66M below for hudson and bolton */ |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 130 | #define SPI_CNTRL1_SPEED_MASK (BIT(15) | BIT(14) | BIT(13) | BIT(12)) |
Marshall Dawson | c1f3233 | 2017-04-21 13:54:08 -0600 | [diff] [blame] | 131 | #define SPI_NORM_SPEED_SH 12 |
| 132 | #define SPI_FAST_SPEED_SH 8 |
Marshall Dawson | 7b0b9f0 | 2017-01-29 17:29:46 -0700 | [diff] [blame] | 133 | |
Marshall Dawson | c1f3233 | 2017-04-21 13:54:08 -0600 | [diff] [blame] | 134 | #define SPI100_ENABLE 0x20 |
| 135 | #define SPI_USE_SPI100 BIT(0) |
Marshall Dawson | 7b0b9f0 | 2017-01-29 17:29:46 -0700 | [diff] [blame] | 136 | |
Marshall Dawson | c1f3233 | 2017-04-21 13:54:08 -0600 | [diff] [blame] | 137 | #define SPI100_SPEED_CONFIG 0x22 |
| 138 | #define SPI_SPEED_66M (0x0) |
| 139 | #define SPI_SPEED_33M ( BIT(0)) |
| 140 | #define SPI_SPEED_22M ( BIT(1) ) |
| 141 | #define SPI_SPEED_16M ( BIT(1) | BIT(0)) |
| 142 | #define SPI_SPEED_100M (BIT(2) ) |
| 143 | #define SPI_SPEED_800K (BIT(2) | BIT(0)) |
| 144 | #define SPI_NORM_SPEED_NEW_SH 12 |
| 145 | #define SPI_FAST_SPEED_NEW_SH 8 |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 146 | #define SPI_ALT_SPEED_NEW_SH 4 |
Marshall Dawson | c1f3233 | 2017-04-21 13:54:08 -0600 | [diff] [blame] | 147 | #define SPI_TPM_SPEED_NEW_SH 0 |
Marshall Dawson | 7b0b9f0 | 2017-01-29 17:29:46 -0700 | [diff] [blame] | 148 | |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 149 | #define SPI100_HOST_PREF_CONFIG 0x2c |
Marshall Dawson | c1f3233 | 2017-04-21 13:54:08 -0600 | [diff] [blame] | 150 | #define SPI_RD4DW_EN_HOST BIT(15) |
Marshall Dawson | 7b0b9f0 | 2017-01-29 17:29:46 -0700 | [diff] [blame] | 151 | |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 152 | static inline int hudson_sata_enable(void) |
| 153 | { |
| 154 | /* True if IDE or AHCI. */ |
| 155 | return (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 2); |
| 156 | } |
| 157 | |
| 158 | static inline int hudson_ide_enable(void) |
| 159 | { |
| 160 | /* True if IDE or LEGACY IDE. */ |
| 161 | return (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 3); |
| 162 | } |
| 163 | |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 164 | void hudson_lpc_port80(void); |
Dave Frodin | f364fc7 | 2015-03-13 08:22:17 -0600 | [diff] [blame] | 165 | void hudson_lpc_decode(void); |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 166 | void hudson_pci_port80(void); |
| 167 | void hudson_clk_output_48Mhz(void); |
Marshall Dawson | 91dea4a | 2017-02-10 16:03:54 -0700 | [diff] [blame] | 168 | void hudson_read_mode(u32 mode); |
| 169 | void hudson_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm); |
| 170 | void hudson_disable_4dw_burst(void); |
| 171 | void hudson_set_readspeed(u16 norm, u16 fast); |
Marc Jones | f962aa5 | 2017-03-22 18:47:49 +0800 | [diff] [blame] | 172 | void lpc_wideio_512_window(uint16_t base); |
| 173 | void lpc_wideio_16_window(uint16_t base); |
Marc Jones | 6fcaaef | 2017-04-20 16:48:42 -0600 | [diff] [blame] | 174 | void hudson_tpm_decode_spi(void); |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 175 | |
Elyes HAOUAS | d9ef546 | 2018-05-19 17:08:23 +0200 | [diff] [blame] | 176 | void hudson_enable(struct device *dev); |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 177 | void s3_resume_init_data(void *FchParams); |
| 178 | |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 179 | #endif /* HUDSON_H */ |