| Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
| 5 | * Copyright (C) 2014 Sage Electronic Engineering, LLC |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #ifndef HUDSON_H |
| 22 | #define HUDSON_H |
| 23 | |
| 24 | #include <device/pci_ids.h> |
| 25 | #include <device/device.h> |
| 26 | #include "chip.h" |
| 27 | |
| 28 | /* Power management index/data registers */ |
| 29 | #define BIOSRAM_INDEX 0xcd4 |
| 30 | #define BIOSRAM_DATA 0xcd5 |
| 31 | #define PM_INDEX 0xcd6 |
| 32 | #define PM_DATA 0xcd7 |
| 33 | #define PM2_INDEX 0xcd0 |
| 34 | #define PM2_DATA 0xcd1 |
| 35 | |
| 36 | #define HUDSON_ACPI_IO_BASE 0x800 |
| 37 | |
| 38 | #define ACPI_PM_EVT_BLK (HUDSON_ACPI_IO_BASE + 0x00) /* 4 bytes */ |
| 39 | #define ACPI_PM1_CNT_BLK (HUDSON_ACPI_IO_BASE + 0x04) /* 2 bytes */ |
| 40 | #define ACPI_PM_TMR_BLK (HUDSON_ACPI_IO_BASE + 0x18) /* 4 bytes */ |
| 41 | #define ACPI_GPE0_BLK (HUDSON_ACPI_IO_BASE + 0x10) /* 8 bytes */ |
| 42 | #define ACPI_CPU_CONTROL (HUDSON_ACPI_IO_BASE + 0x08) /* 6 bytes */ |
| 43 | |
| 44 | #define ACPI_SMI_CTL_PORT 0xb2 |
| 45 | #define ACPI_SMI_CMD_CST_CONTROL 0xde |
| 46 | #define ACPI_SMI_CMD_PST_CONTROL 0xad |
| 47 | #define ACPI_SMI_CMD_DISABLE 0xbe |
| 48 | #define ACPI_SMI_CMD_ENABLE 0xef |
| 49 | #define ACPI_SMI_CMD_S4_REQ 0xc0 |
| 50 | |
| 51 | #define REV_HUDSON_A11 0x11 |
| 52 | #define REV_HUDSON_A12 0x12 |
| 53 | |
| 54 | #define SPIROM_BASE_ADDRESS_REGISTER 0xA0 |
| 55 | #define SPI_ROM_ENABLE 0x02 |
| 56 | #define SPI_BASE_ADDRESS 0xFEC10000 |
| 57 | |
| 58 | static inline int hudson_sata_enable(void) |
| 59 | { |
| 60 | /* True if IDE or AHCI. */ |
| 61 | return (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 2); |
| 62 | } |
| 63 | |
| 64 | static inline int hudson_ide_enable(void) |
| 65 | { |
| 66 | /* True if IDE or LEGACY IDE. */ |
| 67 | return (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 3); |
| 68 | } |
| 69 | |
| 70 | #ifndef __SMM__ |
| 71 | |
| 72 | void pm_write8(u8 reg, u8 value); |
| 73 | u8 pm_read8(u8 reg); |
| 74 | void pm_write16(u8 reg, u16 value); |
| 75 | u16 pm_read16(u16 reg); |
| 76 | |
| 77 | #ifdef __PRE_RAM__ |
| 78 | void hudson_lpc_port80(void); |
| 79 | void hudson_pci_port80(void); |
| 80 | void hudson_clk_output_48Mhz(void); |
| 81 | |
| 82 | int s3_save_nvram_early(u32 dword, int size, int nvram_pos); |
| 83 | int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); |
| 84 | |
| 85 | #else |
| 86 | void hudson_enable(device_t dev); |
| 87 | void s3_resume_init_data(void *FchParams); |
| 88 | |
| 89 | #endif /* __PRE_RAM__ */ |
| 90 | #endif /* __SMM__ */ |
| 91 | |
| 92 | #endif /* HUDSON_H */ |