Michael Niewöhner | 0a6c62f | 2019-09-18 16:31:50 +0200 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
Michael Niewöhner | 0a6c62f | 2019-09-18 16:31:50 +0200 | [diff] [blame] | 3 | # FSP Configuration |
Michael Niewöhner | 0a6c62f | 2019-09-18 16:31:50 +0200 | [diff] [blame] | 4 | register "SkipExtGfxScan" = "1" |
Michael Niewöhner | 0a6c62f | 2019-09-18 16:31:50 +0200 | [diff] [blame] | 5 | |
Michael Niewöhner | 0a6c62f | 2019-09-18 16:31:50 +0200 | [diff] [blame] | 6 | # SATA configuration |
Michael Niewöhner | 0a6c62f | 2019-09-18 16:31:50 +0200 | [diff] [blame] | 7 | register "SataSalpSupport" = "1" |
| 8 | register "SataPortsEnable" = "{ \ |
| 9 | [0] = 1, \ |
| 10 | [1] = 1, \ |
| 11 | [2] = 1, \ |
| 12 | [3] = 1, \ |
| 13 | [4] = 1, \ |
| 14 | [5] = 1, \ |
| 15 | [6] = 1, \ |
| 16 | [7] = 1, \ |
| 17 | }" |
| 18 | |
Michael Niewöhner | 0a6c62f | 2019-09-18 16:31:50 +0200 | [diff] [blame] | 19 | # LPC |
| 20 | register "serirq_mode" = "SERIRQ_CONTINUOUS" |
| 21 | |
Michael Niewöhner | 1b79b86 | 2019-10-20 00:01:58 +0200 | [diff] [blame] | 22 | # Enabling SLP_S0, SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch |
| 23 | register "s0ix_enable" = "1" |
Michael Niewöhner | 0a6c62f | 2019-09-18 16:31:50 +0200 | [diff] [blame] | 24 | register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS" |
| 25 | register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S" |
| 26 | register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S" |
| 27 | register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S" |
| 28 | |
Arthur Heymans | 69cd729 | 2022-11-07 13:52:11 +0100 | [diff] [blame^] | 29 | device cpu_cluster 0 on end |
Michael Niewöhner | 0a6c62f | 2019-09-18 16:31:50 +0200 | [diff] [blame] | 30 | device domain 0 on |
| 31 | device pci 00.0 on end # Host Bridge |
| 32 | device pci 01.0 off end # CPU PCIe Port 10 (x16) |
| 33 | device pci 01.1 off end # CPU PCIe Port 11 (x8) |
| 34 | device pci 01.2 off end # CPU PCIe Port 12 (x4) |
| 35 | device pci 02.0 off end # Integrated Graphics Device (IGD) |
| 36 | device pci 04.0 on end # SA thermal subsystem |
| 37 | device pci 05.0 off end # Imaging Unit |
| 38 | device pci 08.0 off end # Gaussion Mixture Model (GMM) |
| 39 | device pci 13.0 off end # Integrated Sensor Hub |
| 40 | device pci 14.0 on end # USB xHCI |
| 41 | device pci 14.1 off end # USB xDCI (OTG) |
| 42 | device pci 14.2 on end # Thermal Subsystem |
| 43 | device pci 15.0 off end # I2C #0 |
| 44 | device pci 15.1 off end # I2C #1 |
| 45 | device pci 15.2 off end # I2C #2 |
| 46 | device pci 15.3 off end # I2C #3 |
| 47 | device pci 16.0 on end # Management Engine Interface 1 |
| 48 | device pci 16.1 off end # Management Engine Interface 2 |
| 49 | device pci 16.2 off end # Management Engine IDE-R |
| 50 | device pci 16.3 off end # Management Engine KT Redirection |
| 51 | device pci 16.4 off end # Management Engine Interface 3 |
| 52 | device pci 17.0 on end # SATA |
| 53 | device pci 19.0 off end # UART #2 |
| 54 | device pci 19.1 off end # I2C #5 |
| 55 | device pci 19.2 off end # I2C #4 |
| 56 | device pci 1b.0 off end # PCH PCIe Port 17 |
| 57 | device pci 1b.1 off end # PCH PCIe Port 18 |
| 58 | device pci 1b.2 off end # PCH PCIe Port 19 |
| 59 | device pci 1b.3 off end # PCH PCIe Port 20 |
| 60 | device pci 1c.0 off end # PCH PCIe Port 1 |
| 61 | device pci 1c.1 off end # PCH PCIe Port 2 |
| 62 | device pci 1c.2 off end # PCH PCIe Port 3 |
| 63 | device pci 1c.3 off end # PCH PCIe Port 4 |
| 64 | device pci 1c.4 off end # PCH PCIe Port 5 |
| 65 | device pci 1c.5 off end # PCH PCIe Port 6 |
| 66 | device pci 1c.6 off end # PCH PCIe Port 7 |
| 67 | device pci 1c.7 off end # PCH PCIe Port 8 |
| 68 | device pci 1d.0 off end # PCH PCIe Port 9 |
| 69 | device pci 1d.1 off end # PCH PCIe Port 10 |
| 70 | device pci 1d.2 off end # PCH PCIe Port 11 |
| 71 | device pci 1d.3 off end # PCH PCIe Port 12 |
| 72 | device pci 1d.4 off end # PCH PCIe Port 13 |
| 73 | device pci 1d.5 off end # PCH PCIe Port 14 |
| 74 | device pci 1d.6 off end # PCH PCIe Port 15 |
| 75 | device pci 1d.7 off end # PCH PCIe Port 16 |
| 76 | device pci 1e.0 off end # UART #0 |
| 77 | device pci 1e.1 off end # UART #1 |
| 78 | device pci 1e.2 off end # SPI #0 |
Felix Singer | 5291952 | 2020-07-29 21:44:36 +0200 | [diff] [blame] | 79 | device pci 1e.6 off end # SDXC |
Michael Niewöhner | 0a6c62f | 2019-09-18 16:31:50 +0200 | [diff] [blame] | 80 | device pci 1f.0 on # LPC Interface |
| 81 | chip superio/common |
| 82 | device pnp 2e.0 on end |
| 83 | end |
| 84 | chip drivers/pc80/tpm # TPM |
| 85 | device pnp 0c31.0 on end |
| 86 | end |
| 87 | end |
| 88 | device pci 1f.1 on end # P2SB |
| 89 | device pci 1f.2 on end # Power Management Controller |
| 90 | device pci 1f.3 off end # Intel HDA |
| 91 | device pci 1f.4 on end # SMBus |
| 92 | device pci 1f.5 on end # SPI Controller |
| 93 | device pci 1f.6 off end # GbE |
| 94 | device pci 1f.7 off end # Intel Trace Hub |
| 95 | end |
| 96 | end |