Mario Scheithauer | 58bf3e7 | 2018-10-30 09:57:44 +0100 | [diff] [blame] | 1 | chip soc/intel/apollolake |
| 2 | |
Arthur Heymans | 69cd729 | 2022-11-07 13:52:11 +0100 | [diff] [blame^] | 3 | device cpu_cluster 0 on end |
Mario Scheithauer | 58bf3e7 | 2018-10-30 09:57:44 +0100 | [diff] [blame] | 4 | |
| 5 | register "sci_irq" = "SCIS_IRQ10" |
| 6 | |
Mario Scheithauer | 58bf3e7 | 2018-10-30 09:57:44 +0100 | [diff] [blame] | 7 | # EMMC TX DATA Delay 1 |
| 8 | # Refer to EDS-Vol2-22.3. |
| 9 | # [14:8] steps of delay for HS400, each 125ps. |
| 10 | # [6:0] steps of delay for SDR104/HS200, each 125ps. |
| 11 | register "emmc_tx_data_cntl1" = "0x0C16" |
| 12 | |
| 13 | # EMMC TX DATA Delay 2 |
| 14 | # Refer to EDS-Vol2-22.3. |
| 15 | # [30:24] steps of delay for SDR50, each 125ps. |
| 16 | # [22:16] steps of delay for DDR50, each 125ps. |
| 17 | # [14:8] steps of delay for SDR25/HS50, each 125ps. |
| 18 | # [6:0] steps of delay for SDR12, each 125ps. |
| 19 | register "emmc_tx_data_cntl2" = "0x28162828" |
| 20 | |
| 21 | # EMMC RX CMD/DATA Delay 1 |
| 22 | # Refer to EDS-Vol2-22.3. |
| 23 | # [30:24] steps of delay for SDR50, each 125ps. |
| 24 | # [22:16] steps of delay for DDR50, each 125ps. |
| 25 | # [14:8] steps of delay for SDR25/HS50, each 125ps. |
| 26 | # [6:0] steps of delay for SDR12, each 125ps. |
| 27 | register "emmc_rx_cmd_data_cntl1" = "0x00181717" |
| 28 | |
| 29 | # EMMC RX CMD/DATA Delay 2 |
| 30 | # Refer to EDS-Vol2-22.3. |
| 31 | # [17:16] stands for Rx Clock before Output Buffer |
| 32 | # [14:8] steps of delay for Auto Tuning Mode, each 125ps. |
| 33 | # [6:0] steps of delay for HS200, each 125ps. |
| 34 | register "emmc_rx_cmd_data_cntl2" = "0x10008" |
| 35 | |
| 36 | # 0:HS400(Default), 1:HS200, 2:DDR50 |
Mario Scheithauer | 1f21a96 | 2019-07-10 13:15:54 +0200 | [diff] [blame] | 37 | register "emmc_host_max_speed" = "1" |
Mario Scheithauer | 58bf3e7 | 2018-10-30 09:57:44 +0100 | [diff] [blame] | 38 | |
Werner Zeh | 45f4494 | 2021-04-27 11:40:17 +0200 | [diff] [blame] | 39 | # I2C0 controller used for RTC |
| 40 | register "common_soc_config" = "{ |
| 41 | .i2c[0] = { |
| 42 | .speed = I2C_SPEED_STANDARD, |
| 43 | .rise_time_ns = 40, |
| 44 | .fall_time_ns = 10, |
Werner Zeh | a67bda3 | 2021-05-31 07:15:36 +0200 | [diff] [blame] | 45 | .data_hold_time_ns = 300, |
| 46 | .speed_config[0] = { |
| 47 | .speed = I2C_SPEED_FAST, |
| 48 | .scl_hcnt = 0x68, |
| 49 | .scl_lcnt = 0xd1, |
| 50 | .sda_hold = 0x28 |
| 51 | }, |
Werner Zeh | 45f4494 | 2021-04-27 11:40:17 +0200 | [diff] [blame] | 52 | }, |
| 53 | }" |
| 54 | |
Mario Scheithauer | 58bf3e7 | 2018-10-30 09:57:44 +0100 | [diff] [blame] | 55 | device domain 0 on |
| 56 | device pci 00.0 on end # - Host Bridge |
| 57 | device pci 00.1 off end # - DPTF |
| 58 | device pci 00.2 off end # - NPK |
| 59 | device pci 02.0 on end # - Gen - Display |
| 60 | device pci 03.0 off end # - Iunit |
| 61 | device pci 0d.0 on end # - P2SB |
| 62 | device pci 0d.1 off end # - PMC |
| 63 | device pci 0d.2 on end # - SPI |
| 64 | device pci 0d.3 off end # - Shared SRAM |
Werner Zeh | a4e5236 | 2019-04-12 09:10:27 +0200 | [diff] [blame] | 65 | device pci 0e.0 on end # - Audio |
Subrata Banik | e9b9373 | 2020-09-17 15:48:54 +0530 | [diff] [blame] | 66 | device pci 0f.0 on end # - CSE |
Mario Scheithauer | 58bf3e7 | 2018-10-30 09:57:44 +0100 | [diff] [blame] | 67 | device pci 11.0 on end # - ISH |
Mario Scheithauer | f023270 | 2022-01-26 11:53:00 +0100 | [diff] [blame] | 68 | device pci 12.0 on # - SATA |
Sean Rhodes | 5777995 | 2022-05-19 15:35:31 +0100 | [diff] [blame] | 69 | register "SataPortsEnable[0]" = "1" |
| 70 | register "SataPortsEnable[1]" = "1" |
Mario Scheithauer | f023270 | 2022-01-26 11:53:00 +0100 | [diff] [blame] | 71 | register "DisableSataSalpSupport" = "1" |
| 72 | end |
Mario Scheithauer | 92e4ed1 | 2021-01-14 14:54:38 +0100 | [diff] [blame] | 73 | device pci 13.0 on # - RP 2 - PCIe A 0 |
| 74 | register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" |
| 75 | register "pcie_rp_hotplug_enable[2]" = "0" |
| 76 | end |
| 77 | device pci 13.1 on # - RP 3 - PCIe A 1 |
| 78 | register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" |
| 79 | register "pcie_rp_hotplug_enable[3]" = "0" |
| 80 | end |
| 81 | device pci 13.2 on # - RP 4 - PCIe-A 2 |
| 82 | register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" |
| 83 | register "pcie_rp_hotplug_enable[4]" = "0" |
| 84 | end |
| 85 | device pci 13.3 on # - RP 5 - PCIe-A 3 |
| 86 | register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" |
| 87 | register "pcie_rp_hotplug_enable[5]" = "0" |
| 88 | end |
| 89 | device pci 14.0 on # - RP 0 - PCIe-B 0 |
| 90 | register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" |
| 91 | register "pcie_rp_hotplug_enable[0]" = "0" |
| 92 | end |
| 93 | device pci 14.1 on # - RP 1 - PCIe-B 1 |
| 94 | register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" |
| 95 | register "pcie_rp_hotplug_enable[1]" = "0" |
| 96 | end |
Mario Scheithauer | 58bf3e7 | 2018-10-30 09:57:44 +0100 | [diff] [blame] | 97 | device pci 15.0 on end # - XHCI |
| 98 | device pci 15.1 off end # - XDCI |
| 99 | device pci 16.0 on # - I2C 0 |
| 100 | # Enable external RTC chip |
| 101 | chip drivers/i2c/rx6110sa |
| 102 | register "pmon_sampling" = "PMON_SAMPL_256_MS" |
| 103 | register "bks_on" = "0" |
| 104 | register "bks_off" = "1" |
| 105 | register "iocut_en" = "1" |
| 106 | register "set_user_date" = "1" |
| 107 | register "user_year" = "04" |
| 108 | register "user_month" = "07" |
| 109 | register "user_day" = "01" |
| 110 | register "user_weekday" = "4" |
| 111 | device i2c 0x32 on end # RTC RX6110 SA |
| 112 | end |
| 113 | end |
| 114 | device pci 16.1 off end # - I2C 1 |
| 115 | device pci 16.2 off end # - I2C 2 |
| 116 | device pci 16.3 off end # - I2C 3 |
| 117 | device pci 17.0 off end # - I2C 4 |
| 118 | device pci 17.1 off end # - I2C 5 |
| 119 | device pci 17.2 off end # - I2C 6 |
Mario Scheithauer | c776609 | 2018-11-06 12:35:26 +0100 | [diff] [blame] | 120 | device pci 17.3 off end # - I2C 7 |
Mario Scheithauer | 58bf3e7 | 2018-10-30 09:57:44 +0100 | [diff] [blame] | 121 | device pci 18.0 on end # - UART 0 |
| 122 | device pci 18.1 on end # - UART 1 |
| 123 | device pci 18.2 on end # - UART 2 |
| 124 | device pci 18.3 on end # - UART 3 |
| 125 | device pci 19.0 off end # - SPI 0 |
| 126 | device pci 19.1 off end # - SPI 1 |
| 127 | device pci 19.2 off end # - SPI 2 |
| 128 | device pci 1a.0 off end # - PWM |
| 129 | device pci 1b.0 off end # - SDCARD |
| 130 | device pci 1c.0 on end # - eMMC |
| 131 | device pci 1d.0 off end # - UFS |
| 132 | device pci 1e.0 off end # - SDIO |
| 133 | device pci 1f.0 on end # - LPC |
| 134 | device pci 1f.1 on end # - SMBUS |
| 135 | end |
| 136 | end |