Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 4 | * Copyright (C) 2012, 2017 Advanced Micro Devices, Inc. |
| 5 | * Copyright (C) 2014 Google Inc. |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | /* |
| 18 | * ACPI - create the Fixed ACPI Description Tables (FADT) |
| 19 | */ |
| 20 | |
| 21 | #include <string.h> |
| 22 | #include <console/console.h> |
| 23 | #include <arch/acpi.h> |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 24 | #include <arch/acpigen.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 25 | #include <device/pci_ops.h> |
Marc Jones | 5ebc865 | 2017-06-19 23:34:04 -0600 | [diff] [blame] | 26 | #include <arch/ioapic.h> |
Marshall Dawson | e9b862e | 2017-09-22 15:14:46 -0600 | [diff] [blame] | 27 | #include <cpu/x86/smm.h> |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 28 | #include <cbmem.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 29 | #include <device/device.h> |
Marc Jones | 6bfcf66 | 2017-08-06 17:42:35 -0600 | [diff] [blame] | 30 | #include <device/pci.h> |
Marshall Dawson | 69486ca | 2019-05-02 12:03:45 -0600 | [diff] [blame^] | 31 | #include <amdblocks/acpimmio.h> |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 32 | #include <soc/acpi.h> |
Chris Ching | 6a35fab | 2017-10-19 11:45:30 -0600 | [diff] [blame] | 33 | #include <soc/pci_devs.h> |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 34 | #include <soc/southbridge.h> |
Patrick Georgi | 4fbefc5 | 2018-10-23 14:35:37 +0200 | [diff] [blame] | 35 | #include <soc/northbridge.h> |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 36 | #include <soc/nvs.h> |
Richard Spiegel | 93459d6 | 2018-05-16 14:08:33 -0700 | [diff] [blame] | 37 | #include <soc/gpio.h> |
Elyes HAOUAS | 26071aa | 2019-02-15 08:21:33 +0100 | [diff] [blame] | 38 | #include <version.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 39 | |
Marc Jones | 5ebc865 | 2017-06-19 23:34:04 -0600 | [diff] [blame] | 40 | unsigned long acpi_fill_madt(unsigned long current) |
| 41 | { |
| 42 | /* create all subtables for processors */ |
| 43 | current = acpi_create_madt_lapics(current); |
| 44 | |
| 45 | /* Write Kern IOAPIC, only one */ |
| 46 | current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, |
| 47 | CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); |
| 48 | |
| 49 | current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, |
| 50 | CONFIG_MAX_CPUS+1, IO_APIC2_ADDR, 24); |
| 51 | |
| 52 | /* 0: mean bus 0--->ISA */ |
| 53 | /* 0: PIC 0 */ |
| 54 | /* 2: APIC 2 */ |
| 55 | /* 5 mean: 0101 --> Edge-triggered, Active high */ |
| 56 | current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) |
| 57 | current, 0, 0, 2, 0); |
| 58 | current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) |
Marshall Dawson | ecce847 | 2018-10-05 15:41:03 -0600 | [diff] [blame] | 59 | current, 0, 9, 9, 0xf); |
Marc Jones | 5ebc865 | 2017-06-19 23:34:04 -0600 | [diff] [blame] | 60 | |
| 61 | /* create all subtables for processors */ |
| 62 | current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, |
| 63 | 0xff, 5, 1); |
| 64 | /* 1: LINT1 connect to NMI */ |
| 65 | |
| 66 | return current; |
| 67 | } |
| 68 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 69 | /* |
| 70 | * Reference section 5.2.9 Fixed ACPI Description Table (FADT) |
| 71 | * in the ACPI 3.0b specification. |
| 72 | */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 73 | void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 74 | { |
| 75 | acpi_header_t *header = &(fadt->header); |
| 76 | |
| 77 | printk(BIOS_DEBUG, "pm_base: 0x%04x\n", STONEYRIDGE_ACPI_IO_BASE); |
| 78 | |
| 79 | /* Prepare the header */ |
| 80 | memset((void *)fadt, 0, sizeof(acpi_fadt_t)); |
| 81 | memcpy(header->signature, "FACP", 4); |
| 82 | header->length = sizeof(acpi_fadt_t); |
Marc Jones | f9ea7ed | 2018-08-22 18:59:26 -0600 | [diff] [blame] | 83 | header->revision = get_acpi_table_revision(FADT); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 84 | memcpy(header->oem_id, OEM_ID, 6); |
| 85 | memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); |
| 86 | memcpy(header->asl_compiler_id, ASLC, 4); |
Elyes HAOUAS | 26071aa | 2019-02-15 08:21:33 +0100 | [diff] [blame] | 87 | header->asl_compiler_revision = asl_revision; |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 88 | |
| 89 | fadt->firmware_ctrl = (u32) facs; |
| 90 | fadt->dsdt = (u32) dsdt; |
Elyes HAOUAS | 0d4de2a | 2019-02-28 13:04:29 +0100 | [diff] [blame] | 91 | fadt->reserved = 0; /* reserved, should be 0 ACPI 3.0 */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 92 | fadt->preferred_pm_profile = FADT_PM_PROFILE; |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 93 | fadt->sci_int = 9; /* IRQ 09 - ACPI SCI */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 94 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 95 | if (CONFIG(HAVE_SMI_HANDLER)) { |
Marshall Dawson | e9b862e | 2017-09-22 15:14:46 -0600 | [diff] [blame] | 96 | fadt->smi_cmd = APM_CNT; |
| 97 | fadt->acpi_enable = APM_CNT_ACPI_ENABLE; |
| 98 | fadt->acpi_disable = APM_CNT_ACPI_DISABLE; |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 99 | fadt->s4bios_req = 0; /* Not supported */ |
| 100 | fadt->pstate_cnt = 0; /* Not supported */ |
| 101 | fadt->cst_cnt = 0; /* Not supported */ |
Richard Spiegel | e24d795 | 2018-10-26 13:25:01 -0700 | [diff] [blame] | 102 | acpi_write32(MMIO_ACPI_PM1_CNT_BLK, 0); /* clear SCI_EN */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 103 | } else { |
| 104 | fadt->smi_cmd = 0; /* disable system management mode */ |
| 105 | fadt->acpi_enable = 0; /* unused if SMI_CMD = 0 */ |
| 106 | fadt->acpi_disable = 0; /* unused if SMI_CMD = 0 */ |
| 107 | fadt->s4bios_req = 0; /* unused if SMI_CMD = 0 */ |
| 108 | fadt->pstate_cnt = 0; /* unused if SMI_CMD = 0 */ |
| 109 | fadt->cst_cnt = 0x00; /* unused if SMI_CMD = 0 */ |
Richard Spiegel | e24d795 | 2018-10-26 13:25:01 -0700 | [diff] [blame] | 110 | acpi_write32(MMIO_ACPI_PM1_CNT_BLK, 1); /* set SCI_EN */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 111 | } |
| 112 | |
| 113 | fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; |
| 114 | fadt->pm1b_evt_blk = 0x0000; |
| 115 | fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; |
| 116 | fadt->pm1b_cnt_blk = 0x0000; |
| 117 | fadt->pm2_cnt_blk = 0x0000; |
| 118 | fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; |
| 119 | fadt->gpe0_blk = ACPI_GPE0_BLK; |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 120 | fadt->gpe1_blk = 0x0000; /* No gpe1 block */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 121 | |
| 122 | fadt->pm1_evt_len = 4; /* 32 bits */ |
| 123 | fadt->pm1_cnt_len = 2; /* 16 bits */ |
| 124 | fadt->pm2_cnt_len = 0; |
| 125 | fadt->pm_tmr_len = 4; /* 32 bits */ |
| 126 | fadt->gpe0_blk_len = 8; /* 64 bits */ |
| 127 | fadt->gpe1_blk_len = 0; |
| 128 | fadt->gpe1_base = 0; |
| 129 | |
| 130 | fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; |
| 131 | fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; |
| 132 | fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */ |
| 133 | fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */ |
| 134 | fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */ |
| 135 | fadt->duty_width = 3; /* CLK_VAL bits 3:1 */ |
| 136 | fadt->day_alrm = 0; /* 0x7d these have to be */ |
| 137 | fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ |
| 138 | fadt->century = 0; /* 0x7f to make rtc alarm work */ |
| 139 | fadt->iapc_boot_arch = FADT_BOOT_ARCH; /* See table 5-10 */ |
| 140 | fadt->res2 = 0; /* reserved, MUST be 0 ACPI 3.0 */ |
| 141 | fadt->flags = ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */ |
| 142 | ACPI_FADT_C1_SUPPORTED | |
| 143 | ACPI_FADT_SLEEP_BUTTON | |
| 144 | ACPI_FADT_S4_RTC_WAKE | |
| 145 | ACPI_FADT_32BIT_TIMER | |
| 146 | ACPI_FADT_RESET_REGISTER | |
| 147 | ACPI_FADT_PCI_EXPRESS_WAKE | |
| 148 | ACPI_FADT_PLATFORM_CLOCK | |
| 149 | ACPI_FADT_S4_RTC_VALID | |
| 150 | ACPI_FADT_REMOTE_POWER_ON; |
| 151 | |
| 152 | /* Format is from 5.2.3.1: Generic Address Structure */ |
| 153 | /* reset_reg: see section 4.7.3.6 ACPI 3.0a spec */ |
| 154 | /* 8 bit write of value 0x06 to 0xCF9 in IO space */ |
| 155 | fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; |
| 156 | fadt->reset_reg.bit_width = 8; |
| 157 | fadt->reset_reg.bit_offset = 0; |
| 158 | fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 159 | fadt->reset_reg.addrl = SYS_RESET; |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 160 | fadt->reset_reg.addrh = 0x0; |
| 161 | |
| 162 | fadt->reset_value = 6; |
| 163 | |
Elyes HAOUAS | f5b974e | 2018-11-10 20:29:08 +0100 | [diff] [blame] | 164 | fadt->ARM_boot_arch = 0; /* MUST be 0 ACPI 3.0 */ |
| 165 | fadt->FADT_MinorVersion = 0; /* MUST be 0 ACPI 3.0 */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 166 | |
| 167 | fadt->x_firmware_ctl_l = 0; /* set to 0 if firmware_ctrl is used */ |
| 168 | fadt->x_firmware_ctl_h = 0; |
| 169 | fadt->x_dsdt_l = (u32) dsdt; |
| 170 | fadt->x_dsdt_h = 0; |
| 171 | |
| 172 | fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 173 | fadt->x_pm1a_evt_blk.bit_width = 32; |
| 174 | fadt->x_pm1a_evt_blk.bit_offset = 0; |
| 175 | fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; |
| 176 | fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK; |
| 177 | fadt->x_pm1a_evt_blk.addrh = 0x0; |
| 178 | |
| 179 | fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 180 | fadt->x_pm1b_evt_blk.bit_width = 0; |
| 181 | fadt->x_pm1b_evt_blk.bit_offset = 0; |
| 182 | fadt->x_pm1b_evt_blk.access_size = 0; |
| 183 | fadt->x_pm1b_evt_blk.addrl = 0x0; |
| 184 | fadt->x_pm1b_evt_blk.addrh = 0x0; |
| 185 | |
| 186 | |
| 187 | fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 188 | fadt->x_pm1a_cnt_blk.bit_width = 16; |
| 189 | fadt->x_pm1a_cnt_blk.bit_offset = 0; |
| 190 | fadt->x_pm1a_cnt_blk.access_size = 0; |
| 191 | fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; |
| 192 | fadt->x_pm1a_cnt_blk.addrh = 0x0; |
| 193 | |
| 194 | fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 195 | fadt->x_pm1b_cnt_blk.bit_width = 0; |
| 196 | fadt->x_pm1b_cnt_blk.bit_offset = 0; |
| 197 | fadt->x_pm1b_cnt_blk.access_size = 0; |
| 198 | fadt->x_pm1b_cnt_blk.addrl = 0x0; |
| 199 | fadt->x_pm1b_cnt_blk.addrh = 0x0; |
| 200 | |
| 201 | /* |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 202 | * Note: Under this current AMD C state implementation, this is no |
| 203 | * longer used and should not be reported to OS. |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 204 | */ |
| 205 | fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 206 | fadt->x_pm2_cnt_blk.bit_width = 0; |
| 207 | fadt->x_pm2_cnt_blk.bit_offset = 0; |
| 208 | fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; |
| 209 | fadt->x_pm2_cnt_blk.addrl = 0; |
| 210 | fadt->x_pm2_cnt_blk.addrh = 0x0; |
| 211 | |
| 212 | |
| 213 | fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 214 | fadt->x_pm_tmr_blk.bit_width = 32; |
| 215 | fadt->x_pm_tmr_blk.bit_offset = 0; |
| 216 | fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; |
| 217 | fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK; |
| 218 | fadt->x_pm_tmr_blk.addrh = 0x0; |
| 219 | |
| 220 | |
| 221 | fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 222 | fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */ |
| 223 | fadt->x_gpe0_blk.bit_offset = 0; |
| 224 | fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; |
| 225 | fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK; |
| 226 | fadt->x_gpe0_blk.addrh = 0x0; |
| 227 | |
| 228 | |
| 229 | fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 230 | fadt->x_gpe1_blk.bit_width = 0; |
| 231 | fadt->x_gpe1_blk.bit_offset = 0; |
| 232 | fadt->x_gpe1_blk.access_size = 0; |
| 233 | fadt->x_gpe1_blk.addrl = 0; |
| 234 | fadt->x_gpe1_blk.addrh = 0x0; |
| 235 | |
| 236 | header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); |
| 237 | } |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 238 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 239 | void generate_cpu_entries(struct device *device) |
Marc Jones | 6bfcf66 | 2017-08-06 17:42:35 -0600 | [diff] [blame] | 240 | { |
Richard Spiegel | 3f16a0f | 2018-08-06 11:06:08 -0700 | [diff] [blame] | 241 | int cores, cpu; |
Marc Jones | 6bfcf66 | 2017-08-06 17:42:35 -0600 | [diff] [blame] | 242 | |
| 243 | /* Stoney Ridge is single node, just report # of cores */ |
Patrick Georgi | 4fbefc5 | 2018-10-23 14:35:37 +0200 | [diff] [blame] | 244 | cores = pci_read_config32(SOC_NB_DEV, NB_CAPABILITIES2) & CMP_CAP_MASK; |
| 245 | cores++; /* number of cores is CmpCap+1 */ |
Marc Jones | 6bfcf66 | 2017-08-06 17:42:35 -0600 | [diff] [blame] | 246 | |
| 247 | printk(BIOS_DEBUG, "ACPI \\_PR report %d core(s)\n", cores); |
| 248 | |
Marc Jones | e013df9 | 2017-08-23 16:28:02 -0600 | [diff] [blame] | 249 | /* Generate BSP \_PR.P000 */ |
Richard Spiegel | 3f16a0f | 2018-08-06 11:06:08 -0700 | [diff] [blame] | 250 | acpigen_write_processor(0, ACPI_GPE0_BLK, 6); |
Marc Jones | 6bfcf66 | 2017-08-06 17:42:35 -0600 | [diff] [blame] | 251 | acpigen_pop_len(); |
| 252 | |
Marc Jones | e013df9 | 2017-08-23 16:28:02 -0600 | [diff] [blame] | 253 | /* Generate AP \_PR.Pxxx */ |
Marc Jones | 6bfcf66 | 2017-08-06 17:42:35 -0600 | [diff] [blame] | 254 | for (cpu = 1; cpu < cores; cpu++) { |
Richard Spiegel | 3f16a0f | 2018-08-06 11:06:08 -0700 | [diff] [blame] | 255 | acpigen_write_processor(cpu, 0, 0); |
Marc Jones | 6bfcf66 | 2017-08-06 17:42:35 -0600 | [diff] [blame] | 256 | acpigen_pop_len(); |
| 257 | } |
| 258 | } |
| 259 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 260 | unsigned long southbridge_write_acpi_tables(struct device *device, |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 261 | unsigned long current, |
| 262 | struct acpi_rsdp *rsdp) |
| 263 | { |
| 264 | return acpi_write_hpet(device, current, rsdp); |
| 265 | } |
| 266 | |
| 267 | static void acpi_create_gnvs(struct global_nvs_t *gnvs) |
| 268 | { |
| 269 | /* Clear out GNVS. */ |
| 270 | memset(gnvs, 0, sizeof(*gnvs)); |
| 271 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 272 | if (CONFIG(CONSOLE_CBMEM)) |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 273 | gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); |
| 274 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 275 | if (CONFIG(CHROMEOS)) { |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 276 | /* Initialize Verified Boot data */ |
Joel Kitching | 6fbd874 | 2018-08-23 14:56:25 +0800 | [diff] [blame] | 277 | chromeos_init_chromeos_acpi(&gnvs->chromeos); |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 278 | gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; |
| 279 | } |
| 280 | |
| 281 | /* Set unknown wake source */ |
| 282 | gnvs->pm1i = ~0ULL; |
Richard Spiegel | dbee8ae | 2018-05-09 17:34:04 -0700 | [diff] [blame] | 283 | gnvs->gpei = ~0ULL; |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 284 | |
| 285 | /* CPU core count */ |
| 286 | gnvs->pcnt = dev_count_cpu(); |
| 287 | } |
| 288 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 289 | void southbridge_inject_dsdt(struct device *device) |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 290 | { |
| 291 | struct global_nvs_t *gnvs; |
| 292 | |
| 293 | gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 294 | |
| 295 | if (gnvs) { |
| 296 | acpi_create_gnvs(gnvs); |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 297 | |
| 298 | /* Add it to DSDT */ |
| 299 | acpigen_write_scope("\\"); |
| 300 | acpigen_write_name_dword("NVSA", (uintptr_t)gnvs); |
| 301 | acpigen_pop_len(); |
| 302 | } |
| 303 | } |
Richard Spiegel | 93459d6 | 2018-05-16 14:08:33 -0700 | [diff] [blame] | 304 | |
| 305 | static void acpigen_soc_get_gpio_in_local5(uintptr_t addr) |
| 306 | { |
| 307 | /* |
| 308 | * Store (\_SB.GPR2 (addr), Local5) |
| 309 | * \_SB.GPR2 is used to read control byte 2 from control register. |
| 310 | * / It is defined in gpio_lib.asl. |
| 311 | */ |
| 312 | acpigen_write_store(); |
| 313 | acpigen_emit_namestring("\\_SB.GPR2"); |
| 314 | acpigen_write_integer(addr); |
| 315 | acpigen_emit_byte(LOCAL5_OP); |
| 316 | } |
| 317 | |
| 318 | static int acpigen_soc_get_gpio_val(unsigned int gpio_num, uint32_t mask) |
| 319 | { |
| 320 | if (gpio_num >= GPIO_TOTAL_PINS) { |
| 321 | printk(BIOS_WARNING, "Warning: Pin %d should be smaller than" |
| 322 | " %d\n", gpio_num, GPIO_TOTAL_PINS); |
| 323 | return -1; |
| 324 | } |
| 325 | uintptr_t addr = (uintptr_t) gpio_get_address(gpio_num); |
| 326 | |
| 327 | acpigen_soc_get_gpio_in_local5(addr); |
| 328 | |
| 329 | /* If (And (Local5, mask)) */ |
| 330 | acpigen_write_if_and(LOCAL5_OP, mask); |
| 331 | |
| 332 | /* Store (One, Local0) */ |
| 333 | acpigen_write_store_ops(ONE_OP, LOCAL0_OP); |
| 334 | |
| 335 | acpigen_pop_len(); /* If */ |
| 336 | |
| 337 | /* Else */ |
| 338 | acpigen_write_else(); |
| 339 | |
| 340 | /* Store (Zero, Local0) */ |
| 341 | acpigen_write_store_ops(ZERO_OP, LOCAL0_OP); |
| 342 | |
| 343 | acpigen_pop_len(); /* Else */ |
| 344 | |
| 345 | return 0; |
| 346 | } |
| 347 | |
| 348 | static int acpigen_soc_set_gpio_val(unsigned int gpio_num, uint32_t val) |
| 349 | { |
| 350 | if (gpio_num >= GPIO_TOTAL_PINS) { |
| 351 | printk(BIOS_WARNING, "Warning: Pin %d should be smaller than" |
| 352 | " %d\n", gpio_num, GPIO_TOTAL_PINS); |
| 353 | return -1; |
| 354 | } |
| 355 | uintptr_t addr = (uintptr_t) gpio_get_address(gpio_num); |
| 356 | |
Kevin Chiu | d837e66 | 2018-07-03 19:13:34 +0800 | [diff] [blame] | 357 | /* Store (0x40, Local0) */ |
| 358 | acpigen_write_store(); |
| 359 | acpigen_write_integer(GPIO_PIN_OUT); |
| 360 | acpigen_emit_byte(LOCAL0_OP); |
| 361 | |
Richard Spiegel | 93459d6 | 2018-05-16 14:08:33 -0700 | [diff] [blame] | 362 | acpigen_soc_get_gpio_in_local5(addr); |
| 363 | |
| 364 | if (val) { |
| 365 | /* Or (Local5, GPIO_PIN_OUT, Local5) */ |
Kevin Chiu | d837e66 | 2018-07-03 19:13:34 +0800 | [diff] [blame] | 366 | acpigen_write_or(LOCAL5_OP, LOCAL0_OP, LOCAL5_OP); |
Richard Spiegel | 93459d6 | 2018-05-16 14:08:33 -0700 | [diff] [blame] | 367 | } else { |
| 368 | /* Not (GPIO_PIN_OUT, Local6) */ |
Kevin Chiu | d837e66 | 2018-07-03 19:13:34 +0800 | [diff] [blame] | 369 | acpigen_write_not(LOCAL0_OP, LOCAL6_OP); |
Richard Spiegel | 93459d6 | 2018-05-16 14:08:33 -0700 | [diff] [blame] | 370 | |
| 371 | /* And (Local5, Local6, Local5) */ |
| 372 | acpigen_write_and(LOCAL5_OP, LOCAL6_OP, LOCAL5_OP); |
| 373 | } |
| 374 | |
| 375 | /* |
| 376 | * SB.GPW2 (addr, Local5) |
| 377 | * \_SB.GPW2 is used to write control byte in control register |
| 378 | * / byte 2. It is defined in gpio_lib.asl. |
| 379 | */ |
| 380 | acpigen_emit_namestring("\\_SB.GPW2"); |
| 381 | acpigen_write_integer(addr); |
| 382 | acpigen_emit_byte(LOCAL5_OP); |
| 383 | |
| 384 | return 0; |
| 385 | } |
| 386 | |
| 387 | int acpigen_soc_read_rx_gpio(unsigned int gpio_num) |
| 388 | { |
| 389 | return acpigen_soc_get_gpio_val(gpio_num, GPIO_PIN_IN); |
| 390 | } |
| 391 | |
| 392 | int acpigen_soc_get_tx_gpio(unsigned int gpio_num) |
| 393 | { |
| 394 | return acpigen_soc_get_gpio_val(gpio_num, GPIO_PIN_OUT); |
| 395 | } |
| 396 | |
| 397 | int acpigen_soc_set_tx_gpio(unsigned int gpio_num) |
| 398 | { |
| 399 | return acpigen_soc_set_gpio_val(gpio_num, 1); |
| 400 | } |
| 401 | |
| 402 | int acpigen_soc_clear_tx_gpio(unsigned int gpio_num) |
| 403 | { |
| 404 | return acpigen_soc_set_gpio_val(gpio_num, 0); |
| 405 | } |