Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 4 | * Copyright (C) 2012, 2017 Advanced Micro Devices, Inc. |
| 5 | * Copyright (C) 2014 Google Inc. |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | /* |
| 18 | * ACPI - create the Fixed ACPI Description Tables (FADT) |
| 19 | */ |
| 20 | |
| 21 | #include <string.h> |
| 22 | #include <console/console.h> |
| 23 | #include <arch/acpi.h> |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 24 | #include <arch/acpigen.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 25 | #include <arch/io.h> |
Marc Jones | 5ebc865 | 2017-06-19 23:34:04 -0600 | [diff] [blame] | 26 | #include <arch/ioapic.h> |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 27 | #include <cbmem.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 28 | #include <device/device.h> |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 29 | #include <soc/acpi.h> |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame^] | 30 | #include <soc/southbridge.h> |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 31 | #include <soc/nvs.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 32 | #include <soc/smi.h> |
| 33 | |
Marc Jones | 5ebc865 | 2017-06-19 23:34:04 -0600 | [diff] [blame] | 34 | unsigned long acpi_fill_madt(unsigned long current) |
| 35 | { |
| 36 | /* create all subtables for processors */ |
| 37 | current = acpi_create_madt_lapics(current); |
| 38 | |
| 39 | /* Write Kern IOAPIC, only one */ |
| 40 | current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, |
| 41 | CONFIG_MAX_CPUS, IO_APIC_ADDR, 0); |
| 42 | |
| 43 | current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, |
| 44 | CONFIG_MAX_CPUS+1, IO_APIC2_ADDR, 24); |
| 45 | |
| 46 | /* 0: mean bus 0--->ISA */ |
| 47 | /* 0: PIC 0 */ |
| 48 | /* 2: APIC 2 */ |
| 49 | /* 5 mean: 0101 --> Edge-triggered, Active high */ |
| 50 | current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) |
| 51 | current, 0, 0, 2, 0); |
| 52 | current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) |
| 53 | current, 0, 9, 9, 0xF); |
| 54 | |
| 55 | /* create all subtables for processors */ |
| 56 | current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, |
| 57 | 0xff, 5, 1); |
| 58 | /* 1: LINT1 connect to NMI */ |
| 59 | |
| 60 | return current; |
| 61 | } |
| 62 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 63 | /* |
| 64 | * Reference section 5.2.9 Fixed ACPI Description Table (FADT) |
| 65 | * in the ACPI 3.0b specification. |
| 66 | */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 67 | void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 68 | { |
| 69 | acpi_header_t *header = &(fadt->header); |
| 70 | |
| 71 | printk(BIOS_DEBUG, "pm_base: 0x%04x\n", STONEYRIDGE_ACPI_IO_BASE); |
| 72 | |
| 73 | /* Prepare the header */ |
| 74 | memset((void *)fadt, 0, sizeof(acpi_fadt_t)); |
| 75 | memcpy(header->signature, "FACP", 4); |
| 76 | header->length = sizeof(acpi_fadt_t); |
| 77 | header->revision = ACPI_FADT_REV_ACPI_3_0; |
| 78 | memcpy(header->oem_id, OEM_ID, 6); |
| 79 | memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); |
| 80 | memcpy(header->asl_compiler_id, ASLC, 4); |
| 81 | header->asl_compiler_revision = 0; |
| 82 | |
| 83 | fadt->firmware_ctrl = (u32) facs; |
| 84 | fadt->dsdt = (u32) dsdt; |
| 85 | fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ |
| 86 | fadt->preferred_pm_profile = FADT_PM_PROFILE; |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame^] | 87 | fadt->sci_int = 9; /* IRQ 09 - ACPI SCI */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 88 | |
| 89 | if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { |
| 90 | fadt->smi_cmd = ACPI_SMI_CTL_PORT; |
| 91 | fadt->acpi_enable = ACPI_SMI_CMD_ENABLE; |
| 92 | fadt->acpi_disable = ACPI_SMI_CMD_DISABLE; |
| 93 | fadt->s4bios_req = 0; /* Not supported */ |
| 94 | fadt->pstate_cnt = 0; /* Not supported */ |
| 95 | fadt->cst_cnt = 0; /* Not supported */ |
| 96 | outl(0x0, ACPI_PM1_CNT_BLK); /* clear SCI_EN */ |
| 97 | } else { |
| 98 | fadt->smi_cmd = 0; /* disable system management mode */ |
| 99 | fadt->acpi_enable = 0; /* unused if SMI_CMD = 0 */ |
| 100 | fadt->acpi_disable = 0; /* unused if SMI_CMD = 0 */ |
| 101 | fadt->s4bios_req = 0; /* unused if SMI_CMD = 0 */ |
| 102 | fadt->pstate_cnt = 0; /* unused if SMI_CMD = 0 */ |
| 103 | fadt->cst_cnt = 0x00; /* unused if SMI_CMD = 0 */ |
| 104 | outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ |
| 105 | } |
| 106 | |
| 107 | fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; |
| 108 | fadt->pm1b_evt_blk = 0x0000; |
| 109 | fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; |
| 110 | fadt->pm1b_cnt_blk = 0x0000; |
| 111 | fadt->pm2_cnt_blk = 0x0000; |
| 112 | fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; |
| 113 | fadt->gpe0_blk = ACPI_GPE0_BLK; |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame^] | 114 | fadt->gpe1_blk = 0x0000; /* No gpe1 block */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 115 | |
| 116 | fadt->pm1_evt_len = 4; /* 32 bits */ |
| 117 | fadt->pm1_cnt_len = 2; /* 16 bits */ |
| 118 | fadt->pm2_cnt_len = 0; |
| 119 | fadt->pm_tmr_len = 4; /* 32 bits */ |
| 120 | fadt->gpe0_blk_len = 8; /* 64 bits */ |
| 121 | fadt->gpe1_blk_len = 0; |
| 122 | fadt->gpe1_base = 0; |
| 123 | |
| 124 | fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; |
| 125 | fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; |
| 126 | fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */ |
| 127 | fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */ |
| 128 | fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */ |
| 129 | fadt->duty_width = 3; /* CLK_VAL bits 3:1 */ |
| 130 | fadt->day_alrm = 0; /* 0x7d these have to be */ |
| 131 | fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ |
| 132 | fadt->century = 0; /* 0x7f to make rtc alarm work */ |
| 133 | fadt->iapc_boot_arch = FADT_BOOT_ARCH; /* See table 5-10 */ |
| 134 | fadt->res2 = 0; /* reserved, MUST be 0 ACPI 3.0 */ |
| 135 | fadt->flags = ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */ |
| 136 | ACPI_FADT_C1_SUPPORTED | |
| 137 | ACPI_FADT_SLEEP_BUTTON | |
| 138 | ACPI_FADT_S4_RTC_WAKE | |
| 139 | ACPI_FADT_32BIT_TIMER | |
| 140 | ACPI_FADT_RESET_REGISTER | |
| 141 | ACPI_FADT_PCI_EXPRESS_WAKE | |
| 142 | ACPI_FADT_PLATFORM_CLOCK | |
| 143 | ACPI_FADT_S4_RTC_VALID | |
| 144 | ACPI_FADT_REMOTE_POWER_ON; |
| 145 | |
| 146 | /* Format is from 5.2.3.1: Generic Address Structure */ |
| 147 | /* reset_reg: see section 4.7.3.6 ACPI 3.0a spec */ |
| 148 | /* 8 bit write of value 0x06 to 0xCF9 in IO space */ |
| 149 | fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; |
| 150 | fadt->reset_reg.bit_width = 8; |
| 151 | fadt->reset_reg.bit_offset = 0; |
| 152 | fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 153 | fadt->reset_reg.addrl = SYS_RESET; |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 154 | fadt->reset_reg.addrh = 0x0; |
| 155 | |
| 156 | fadt->reset_value = 6; |
| 157 | |
| 158 | fadt->res3 = 0; /* reserved, MUST be 0 ACPI 3.0 */ |
| 159 | fadt->res4 = 0; /* reserved, MUST be 0 ACPI 3.0 */ |
| 160 | fadt->res5 = 0; /* reserved, MUST be 0 ACPI 3.0 */ |
| 161 | |
| 162 | fadt->x_firmware_ctl_l = 0; /* set to 0 if firmware_ctrl is used */ |
| 163 | fadt->x_firmware_ctl_h = 0; |
| 164 | fadt->x_dsdt_l = (u32) dsdt; |
| 165 | fadt->x_dsdt_h = 0; |
| 166 | |
| 167 | fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 168 | fadt->x_pm1a_evt_blk.bit_width = 32; |
| 169 | fadt->x_pm1a_evt_blk.bit_offset = 0; |
| 170 | fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; |
| 171 | fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK; |
| 172 | fadt->x_pm1a_evt_blk.addrh = 0x0; |
| 173 | |
| 174 | fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 175 | fadt->x_pm1b_evt_blk.bit_width = 0; |
| 176 | fadt->x_pm1b_evt_blk.bit_offset = 0; |
| 177 | fadt->x_pm1b_evt_blk.access_size = 0; |
| 178 | fadt->x_pm1b_evt_blk.addrl = 0x0; |
| 179 | fadt->x_pm1b_evt_blk.addrh = 0x0; |
| 180 | |
| 181 | |
| 182 | fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 183 | fadt->x_pm1a_cnt_blk.bit_width = 16; |
| 184 | fadt->x_pm1a_cnt_blk.bit_offset = 0; |
| 185 | fadt->x_pm1a_cnt_blk.access_size = 0; |
| 186 | fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; |
| 187 | fadt->x_pm1a_cnt_blk.addrh = 0x0; |
| 188 | |
| 189 | fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 190 | fadt->x_pm1b_cnt_blk.bit_width = 0; |
| 191 | fadt->x_pm1b_cnt_blk.bit_offset = 0; |
| 192 | fadt->x_pm1b_cnt_blk.access_size = 0; |
| 193 | fadt->x_pm1b_cnt_blk.addrl = 0x0; |
| 194 | fadt->x_pm1b_cnt_blk.addrh = 0x0; |
| 195 | |
| 196 | /* |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 197 | * Note: Under this current AMD C state implementation, this is no |
| 198 | * longer used and should not be reported to OS. |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 199 | */ |
| 200 | fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 201 | fadt->x_pm2_cnt_blk.bit_width = 0; |
| 202 | fadt->x_pm2_cnt_blk.bit_offset = 0; |
| 203 | fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; |
| 204 | fadt->x_pm2_cnt_blk.addrl = 0; |
| 205 | fadt->x_pm2_cnt_blk.addrh = 0x0; |
| 206 | |
| 207 | |
| 208 | fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 209 | fadt->x_pm_tmr_blk.bit_width = 32; |
| 210 | fadt->x_pm_tmr_blk.bit_offset = 0; |
| 211 | fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; |
| 212 | fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK; |
| 213 | fadt->x_pm_tmr_blk.addrh = 0x0; |
| 214 | |
| 215 | |
| 216 | fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 217 | fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */ |
| 218 | fadt->x_gpe0_blk.bit_offset = 0; |
| 219 | fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; |
| 220 | fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK; |
| 221 | fadt->x_gpe0_blk.addrh = 0x0; |
| 222 | |
| 223 | |
| 224 | fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 225 | fadt->x_gpe1_blk.bit_width = 0; |
| 226 | fadt->x_gpe1_blk.bit_offset = 0; |
| 227 | fadt->x_gpe1_blk.access_size = 0; |
| 228 | fadt->x_gpe1_blk.addrl = 0; |
| 229 | fadt->x_gpe1_blk.addrh = 0x0; |
| 230 | |
| 231 | header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); |
| 232 | } |
Marc Jones | 257db58 | 2017-06-18 17:33:30 -0600 | [diff] [blame] | 233 | |
| 234 | unsigned long southbridge_write_acpi_tables(device_t device, |
| 235 | unsigned long current, |
| 236 | struct acpi_rsdp *rsdp) |
| 237 | { |
| 238 | return acpi_write_hpet(device, current, rsdp); |
| 239 | } |
| 240 | |
| 241 | static void acpi_create_gnvs(struct global_nvs_t *gnvs) |
| 242 | { |
| 243 | /* Clear out GNVS. */ |
| 244 | memset(gnvs, 0, sizeof(*gnvs)); |
| 245 | |
| 246 | if (IS_ENABLED(CONFIG_CONSOLE_CBMEM)) |
| 247 | gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); |
| 248 | |
| 249 | if (IS_ENABLED(CONFIG_CHROMEOS)) { |
| 250 | /* Initialize Verified Boot data */ |
| 251 | chromeos_init_vboot(&gnvs->chromeos); |
| 252 | gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; |
| 253 | } |
| 254 | |
| 255 | /* Set unknown wake source */ |
| 256 | gnvs->pm1i = ~0ULL; |
| 257 | |
| 258 | /* CPU core count */ |
| 259 | gnvs->pcnt = dev_count_cpu(); |
| 260 | } |
| 261 | |
| 262 | void southbridge_inject_dsdt(device_t device) |
| 263 | { |
| 264 | struct global_nvs_t *gnvs; |
| 265 | |
| 266 | gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 267 | |
| 268 | if (gnvs) { |
| 269 | acpi_create_gnvs(gnvs); |
| 270 | acpi_save_gnvs((uintptr_t)gnvs); |
| 271 | |
| 272 | /* Add it to DSDT */ |
| 273 | acpigen_write_scope("\\"); |
| 274 | acpigen_write_name_dword("NVSA", (uintptr_t)gnvs); |
| 275 | acpigen_pop_len(); |
| 276 | } |
| 277 | } |