Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2011 The Chromium OS Authors. |
| 3 | * |
| 4 | * See file CREDITS for list of people who contributed to this |
| 5 | * project. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but without any warranty; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 20 | * MA 02111-1307 USA |
| 21 | */ |
| 22 | |
| 23 | /* This file is derived from the flashrom project. */ |
| 24 | #include <stdint.h> |
| 25 | #include <stdlib.h> |
| 26 | #include <string.h> |
| 27 | #include <delay.h> |
| 28 | #include <arch/io.h> |
| 29 | #include <console/console.h> |
| 30 | #include <device/pci.h> |
| 31 | #include <device/pci_ids.h> |
| 32 | |
| 33 | #include <spi.h> |
| 34 | |
| 35 | #define min(a, b) ((a)<(b)?(a):(b)) |
| 36 | |
| 37 | typedef device_t pci_dev_t; |
| 38 | #define pci_read_config_byte(dev, reg, targ) *(targ) = pci_read_config8(dev, reg) |
| 39 | #define pci_read_config_word(dev, reg, targ) *(targ) = pci_read_config16(dev, reg) |
| 40 | #define pci_read_config_dword(dev, reg, targ) *(targ) = pci_read_config32(dev, reg) |
| 41 | #define pci_write_config_byte(dev, reg, val) pci_write_config8(dev, reg, val) |
| 42 | #define pci_write_config_word(dev, reg, val) pci_write_config16(dev, reg, val) |
| 43 | #define pci_write_config_dword(dev, reg, val) pci_write_config32(dev, reg, val) |
| 44 | |
| 45 | typedef struct spi_slave ich_spi_slave; |
| 46 | |
| 47 | static int ichspi_lock = 0; |
| 48 | |
| 49 | typedef struct ich7_spi_regs { |
| 50 | uint16_t spis; |
| 51 | uint16_t spic; |
| 52 | uint32_t spia; |
| 53 | uint64_t spid[8]; |
| 54 | uint64_t _pad; |
| 55 | uint32_t bbar; |
| 56 | uint16_t preop; |
| 57 | uint16_t optype; |
| 58 | uint8_t opmenu[8]; |
| 59 | } __attribute__((packed)) ich7_spi_regs; |
| 60 | |
| 61 | typedef struct ich9_spi_regs { |
| 62 | uint32_t bfpr; |
| 63 | uint16_t hsfs; |
| 64 | uint16_t hsfc; |
| 65 | uint32_t faddr; |
| 66 | uint32_t _reserved0; |
| 67 | uint32_t fdata[16]; |
| 68 | uint32_t frap; |
| 69 | uint32_t freg[5]; |
| 70 | uint32_t _reserved1[3]; |
| 71 | uint32_t pr[5]; |
| 72 | uint32_t _reserved2[2]; |
| 73 | uint8_t ssfs; |
| 74 | uint8_t ssfc[3]; |
| 75 | uint16_t preop; |
| 76 | uint16_t optype; |
| 77 | uint8_t opmenu[8]; |
| 78 | uint32_t bbar; |
| 79 | uint8_t _reserved3[12]; |
| 80 | uint32_t fdoc; |
| 81 | uint32_t fdod; |
| 82 | uint8_t _reserved4[8]; |
| 83 | uint32_t afc; |
| 84 | uint32_t lvscc; |
| 85 | uint32_t uvscc; |
| 86 | uint8_t _reserved5[4]; |
| 87 | uint32_t fpb; |
| 88 | uint8_t _reserved6[28]; |
| 89 | uint32_t srdl; |
| 90 | uint32_t srdc; |
| 91 | uint32_t srd; |
| 92 | } __attribute__((packed)) ich9_spi_regs; |
| 93 | |
| 94 | typedef struct ich_spi_controller { |
| 95 | int locked; |
| 96 | |
| 97 | uint8_t *opmenu; |
| 98 | int menubytes; |
| 99 | uint16_t *preop; |
| 100 | uint16_t *optype; |
| 101 | uint32_t *addr; |
| 102 | uint8_t *data; |
| 103 | unsigned databytes; |
| 104 | uint8_t *status; |
| 105 | uint16_t *control; |
| 106 | uint32_t *bbar; |
| 107 | } ich_spi_controller; |
| 108 | |
| 109 | static ich_spi_controller cntlr; |
| 110 | |
| 111 | enum { |
| 112 | SPIS_SCIP = 0x0001, |
| 113 | SPIS_GRANT = 0x0002, |
| 114 | SPIS_CDS = 0x0004, |
| 115 | SPIS_FCERR = 0x0008, |
| 116 | SSFS_AEL = 0x0010, |
| 117 | SPIS_LOCK = 0x8000, |
| 118 | SPIS_RESERVED_MASK = 0x7ff0, |
| 119 | SSFS_RESERVED_MASK = 0x7fe2 |
| 120 | }; |
| 121 | |
| 122 | enum { |
| 123 | SPIC_SCGO = 0x000002, |
| 124 | SPIC_ACS = 0x000004, |
| 125 | SPIC_SPOP = 0x000008, |
| 126 | SPIC_DBC = 0x003f00, |
| 127 | SPIC_DS = 0x004000, |
| 128 | SPIC_SME = 0x008000, |
| 129 | SSFC_SCF_MASK = 0x070000, |
| 130 | SSFC_RESERVED = 0xf80000 |
| 131 | }; |
| 132 | |
| 133 | enum { |
| 134 | HSFS_FDONE = 0x0001, |
| 135 | HSFS_FCERR = 0x0002, |
| 136 | HSFS_AEL = 0x0004, |
| 137 | HSFS_BERASE_MASK = 0x0018, |
| 138 | HSFS_BERASE_SHIFT = 3, |
| 139 | HSFS_SCIP = 0x0020, |
| 140 | HSFS_FDOPSS = 0x2000, |
| 141 | HSFS_FDV = 0x4000, |
| 142 | HSFS_FLOCKDN = 0x8000 |
| 143 | }; |
| 144 | |
| 145 | enum { |
| 146 | HSFC_FGO = 0x0001, |
| 147 | HSFC_FCYCLE_MASK = 0x0006, |
| 148 | HSFC_FCYCLE_SHIFT = 1, |
| 149 | HSFC_FDBC_MASK = 0x3f00, |
| 150 | HSFC_FDBC_SHIFT = 8, |
| 151 | HSFC_FSMIE = 0x8000 |
| 152 | }; |
| 153 | |
| 154 | enum { |
| 155 | SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0, |
| 156 | SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1, |
| 157 | SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2, |
| 158 | SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 |
| 159 | }; |
| 160 | |
| 161 | #if CONFIG_DEBUG_SPI_FLASH |
| 162 | |
| 163 | static u8 readb_(const void *addr) |
| 164 | { |
Stefan Reinauer | 14b23a6 | 2012-05-22 15:24:51 -0700 | [diff] [blame] | 165 | u8 v = read8((unsigned long)addr); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 166 | printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", |
| 167 | v, ((unsigned) addr & 0xffff) - 0xf020); |
| 168 | return v; |
| 169 | } |
| 170 | |
| 171 | static u16 readw_(const void *addr) |
| 172 | { |
Stefan Reinauer | 14b23a6 | 2012-05-22 15:24:51 -0700 | [diff] [blame] | 173 | u16 v = read16((unsigned long)addr); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 174 | printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", |
| 175 | v, ((unsigned) addr & 0xffff) - 0xf020); |
| 176 | return v; |
| 177 | } |
| 178 | |
| 179 | static u32 readl_(const void *addr) |
| 180 | { |
Stefan Reinauer | 14b23a6 | 2012-05-22 15:24:51 -0700 | [diff] [blame] | 181 | u32 v = read32((unsigned long)addr); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 182 | printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", |
| 183 | v, ((unsigned) addr & 0xffff) - 0xf020); |
| 184 | return v; |
| 185 | } |
| 186 | |
| 187 | static void writeb_(u8 b, const void *addr) |
| 188 | { |
Stefan Reinauer | 14b23a6 | 2012-05-22 15:24:51 -0700 | [diff] [blame] | 189 | write8((unsigned long)addr, b); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 190 | printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", |
| 191 | b, ((unsigned) addr & 0xffff) - 0xf020); |
| 192 | } |
| 193 | |
| 194 | static void writew_(u16 b, const void *addr) |
| 195 | { |
Stefan Reinauer | 14b23a6 | 2012-05-22 15:24:51 -0700 | [diff] [blame] | 196 | write16((unsigned long)addr, b); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 197 | printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", |
| 198 | b, ((unsigned) addr & 0xffff) - 0xf020); |
| 199 | } |
| 200 | |
| 201 | static void writel_(u32 b, const void *addr) |
| 202 | { |
Stefan Reinauer | 14b23a6 | 2012-05-22 15:24:51 -0700 | [diff] [blame] | 203 | write32((unsigned long)addr, b); |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 204 | printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", |
| 205 | b, ((unsigned) addr & 0xffff) - 0xf020); |
| 206 | } |
| 207 | |
| 208 | #else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ |
| 209 | |
| 210 | #define readb_(a) read8((uint32_t)a) |
| 211 | #define readw_(a) read16((uint32_t)a) |
| 212 | #define readl_(a) read32((uint32_t)a) |
| 213 | #define writeb_(val, addr) write8((uint32_t)addr, val) |
| 214 | #define writew_(val, addr) write16((uint32_t)addr, val) |
| 215 | #define writel_(val, addr) write32((uint32_t)addr, val) |
| 216 | |
| 217 | #endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */ |
| 218 | |
| 219 | static void write_reg(const void *value, void *dest, uint32_t size) |
| 220 | { |
| 221 | const uint8_t *bvalue = value; |
| 222 | uint8_t *bdest = dest; |
| 223 | |
| 224 | while (size >= 4) { |
| 225 | writel_(*(const uint32_t *)bvalue, bdest); |
| 226 | bdest += 4; bvalue += 4; size -= 4; |
| 227 | } |
| 228 | while (size) { |
| 229 | writeb_(*bvalue, bdest); |
| 230 | bdest++; bvalue++; size--; |
| 231 | } |
| 232 | } |
| 233 | |
| 234 | static void read_reg(const void *src, void *value, uint32_t size) |
| 235 | { |
| 236 | const uint8_t *bsrc = src; |
| 237 | uint8_t *bvalue = value; |
| 238 | |
| 239 | while (size >= 4) { |
| 240 | *(uint32_t *)bvalue = readl_(bsrc); |
| 241 | bsrc += 4; bvalue += 4; size -= 4; |
| 242 | } |
| 243 | while (size) { |
| 244 | *bvalue = readb_(bsrc); |
| 245 | bsrc++; bvalue++; size--; |
| 246 | } |
| 247 | } |
| 248 | |
| 249 | static void ich_set_bbar(uint32_t minaddr) |
| 250 | { |
| 251 | const uint32_t bbar_mask = 0x00ffff00; |
| 252 | uint32_t ichspi_bbar; |
| 253 | |
| 254 | minaddr &= bbar_mask; |
| 255 | ichspi_bbar = readl_(cntlr.bbar) & ~bbar_mask; |
| 256 | ichspi_bbar |= minaddr; |
| 257 | writel_(ichspi_bbar, cntlr.bbar); |
| 258 | } |
| 259 | |
| 260 | int spi_cs_is_valid(unsigned int bus, unsigned int cs) |
| 261 | { |
| 262 | printk(BIOS_DEBUG, "spi_cs_is_valid used but not implemented\n"); |
| 263 | return 0; |
| 264 | } |
| 265 | |
| 266 | struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, |
| 267 | unsigned int max_hz, unsigned int mode) |
| 268 | { |
| 269 | ich_spi_slave *slave = malloc(sizeof(*slave)); |
| 270 | |
| 271 | if (!slave) { |
| 272 | printk(BIOS_DEBUG, "ICH SPI: Bad allocation\n"); |
| 273 | return NULL; |
| 274 | } |
| 275 | |
| 276 | memset(slave, 0, sizeof(*slave)); |
| 277 | |
| 278 | slave->bus = bus; |
| 279 | slave->cs = cs; |
| 280 | return slave; |
| 281 | } |
| 282 | |
| 283 | void spi_free_slave(struct spi_slave *_slave) |
| 284 | { |
| 285 | ich_spi_slave *slave = (ich_spi_slave *)_slave; |
| 286 | free(slave); |
| 287 | } |
| 288 | |
Stefan Reinauer | 691c9f0 | 2012-05-23 11:18:35 -0700 | [diff] [blame^] | 289 | /* |
| 290 | * Check if this device ID matches one of supported Intel PCH devices. |
| 291 | * |
| 292 | * Return the ICH version if there is a match, or zero otherwise. |
| 293 | */ |
| 294 | static inline int get_ich_version(uint16_t device_id) |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 295 | { |
Stefan Reinauer | 691c9f0 | 2012-05-23 11:18:35 -0700 | [diff] [blame^] | 296 | if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC) |
| 297 | return 7; |
| 298 | |
| 299 | if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN && |
| 300 | device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) || |
| 301 | (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN && |
| 302 | device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX)) |
| 303 | return 9; |
| 304 | |
| 305 | return 0; |
| 306 | } |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 307 | |
| 308 | void spi_init(void) |
| 309 | { |
| 310 | int ich_version = 0; |
| 311 | |
| 312 | uint8_t *rcrb; /* Root Complex Register Block */ |
| 313 | uint32_t rcba; /* Root Complex Base Address */ |
| 314 | uint8_t bios_cntl; |
| 315 | pci_dev_t dev; |
| 316 | uint32_t ids; |
| 317 | uint16_t vendor_id, device_id; |
| 318 | |
| 319 | dev = dev_find_slot(0, PCI_DEVFN(31, 0)); |
| 320 | pci_read_config_dword(dev, 0, &ids); |
| 321 | vendor_id = ids; |
| 322 | device_id = (ids >> 16); |
| 323 | |
| 324 | if (vendor_id != PCI_VENDOR_ID_INTEL) { |
| 325 | printk(BIOS_DEBUG, "ICH SPI: No ICH found.\n"); |
| 326 | return; |
| 327 | } |
| 328 | |
Stefan Reinauer | 691c9f0 | 2012-05-23 11:18:35 -0700 | [diff] [blame^] | 329 | ich_version = get_ich_version(device_id); |
| 330 | |
| 331 | if (!ich_version) { |
Stefan Reinauer | 1c56d9b | 2012-05-10 11:27:32 -0700 | [diff] [blame] | 332 | printk(BIOS_DEBUG, "ICH SPI: No known ICH found.\n"); |
| 333 | return; |
| 334 | } |
| 335 | |
| 336 | pci_read_config_dword(dev, 0xf0, &rcba); |
| 337 | /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */ |
| 338 | rcrb = (uint8_t *)(rcba & 0xffffc000); |
| 339 | switch (ich_version) { |
| 340 | case 7: |
| 341 | { |
| 342 | const uint16_t ich7_spibar_offset = 0x3020; |
| 343 | ich7_spi_regs *ich7_spi = |
| 344 | (ich7_spi_regs *)(rcrb + ich7_spibar_offset); |
| 345 | |
| 346 | ichspi_lock = readw_(&ich7_spi->spis) & SPIS_LOCK; |
| 347 | cntlr.opmenu = ich7_spi->opmenu; |
| 348 | cntlr.menubytes = sizeof(ich7_spi->opmenu); |
| 349 | cntlr.optype = &ich7_spi->optype; |
| 350 | cntlr.addr = &ich7_spi->spia; |
| 351 | cntlr.data = (uint8_t *)ich7_spi->spid; |
| 352 | cntlr.databytes = sizeof(ich7_spi->spid); |
| 353 | cntlr.status = (uint8_t *)&ich7_spi->spis; |
| 354 | cntlr.control = &ich7_spi->spic; |
| 355 | cntlr.bbar = &ich7_spi->bbar; |
| 356 | cntlr.preop = &ich7_spi->preop; |
| 357 | break; |
| 358 | } |
| 359 | case 9: |
| 360 | { |
| 361 | const uint16_t ich9_spibar_offset = 0x3800; |
| 362 | ich9_spi_regs *ich9_spi = |
| 363 | (ich9_spi_regs *)(rcrb + ich9_spibar_offset); |
| 364 | ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN; |
| 365 | cntlr.opmenu = ich9_spi->opmenu; |
| 366 | cntlr.menubytes = sizeof(ich9_spi->opmenu); |
| 367 | cntlr.optype = &ich9_spi->optype; |
| 368 | cntlr.addr = &ich9_spi->faddr; |
| 369 | cntlr.data = (uint8_t *)ich9_spi->fdata; |
| 370 | cntlr.databytes = sizeof(ich9_spi->fdata); |
| 371 | cntlr.status = &ich9_spi->ssfs; |
| 372 | cntlr.control = (uint16_t *)ich9_spi->ssfc; |
| 373 | cntlr.bbar = &ich9_spi->bbar; |
| 374 | cntlr.preop = &ich9_spi->preop; |
| 375 | break; |
| 376 | } |
| 377 | default: |
| 378 | printk(BIOS_DEBUG, "ICH SPI: Unrecognized ICH version %d.\n", ich_version); |
| 379 | } |
| 380 | |
| 381 | ich_set_bbar(0); |
| 382 | |
| 383 | /* Disable the BIOS write protect so write commands are allowed. */ |
| 384 | pci_read_config_byte(dev, 0xdc, &bios_cntl); |
| 385 | switch (ich_version) { |
| 386 | case 9: |
| 387 | /* Deassert SMM BIOS Write Protect Disable. */ |
| 388 | bios_cntl &= ~(1 << 5); |
| 389 | break; |
| 390 | |
| 391 | default: |
| 392 | break; |
| 393 | } |
| 394 | pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1); |
| 395 | } |
| 396 | |
| 397 | int spi_claim_bus(struct spi_slave *slave) |
| 398 | { |
| 399 | /* Handled by ICH automatically. */ |
| 400 | return 0; |
| 401 | } |
| 402 | |
| 403 | void spi_release_bus(struct spi_slave *slave) |
| 404 | { |
| 405 | /* Handled by ICH automatically. */ |
| 406 | } |
| 407 | |
| 408 | void spi_cs_activate(struct spi_slave *slave) |
| 409 | { |
| 410 | /* Handled by ICH automatically. */ |
| 411 | } |
| 412 | |
| 413 | void spi_cs_deactivate(struct spi_slave *slave) |
| 414 | { |
| 415 | /* Handled by ICH automatically. */ |
| 416 | } |
| 417 | |
| 418 | typedef struct spi_transaction { |
| 419 | const uint8_t *out; |
| 420 | uint32_t bytesout; |
| 421 | uint8_t *in; |
| 422 | uint32_t bytesin; |
| 423 | uint8_t type; |
| 424 | uint8_t opcode; |
| 425 | uint32_t offset; |
| 426 | } spi_transaction; |
| 427 | |
| 428 | static inline void spi_use_out(spi_transaction *trans, unsigned bytes) |
| 429 | { |
| 430 | trans->out += bytes; |
| 431 | trans->bytesout -= bytes; |
| 432 | } |
| 433 | |
| 434 | static inline void spi_use_in(spi_transaction *trans, unsigned bytes) |
| 435 | { |
| 436 | trans->in += bytes; |
| 437 | trans->bytesin -= bytes; |
| 438 | } |
| 439 | |
| 440 | static void spi_setup_type(spi_transaction *trans) |
| 441 | { |
| 442 | trans->type = 0xFF; |
| 443 | |
| 444 | /* Try to guess spi type from read/write sizes. */ |
| 445 | if (trans->bytesin == 0) { |
| 446 | if (trans->bytesout > 4) |
| 447 | /* |
| 448 | * If bytesin = 0 and bytesout > 4, we presume this is |
| 449 | * a write data operation, which is accompanied by an |
| 450 | * address. |
| 451 | */ |
| 452 | trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; |
| 453 | else |
| 454 | trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; |
| 455 | return; |
| 456 | } |
| 457 | |
| 458 | if (trans->bytesout == 1) { /* and bytesin is > 0 */ |
| 459 | trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; |
| 460 | return; |
| 461 | } |
| 462 | |
| 463 | if (trans->bytesout == 4) { /* and bytesin is > 0 */ |
| 464 | trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; |
| 465 | } |
| 466 | } |
| 467 | |
| 468 | static int spi_setup_opcode(spi_transaction *trans) |
| 469 | { |
| 470 | uint16_t optypes; |
| 471 | uint8_t opmenu[cntlr.menubytes]; |
| 472 | |
| 473 | trans->opcode = trans->out[0]; |
| 474 | spi_use_out(trans, 1); |
| 475 | if (!ichspi_lock) { |
| 476 | /* The lock is off, so just use index 0. */ |
| 477 | writeb_(trans->opcode, cntlr.opmenu); |
| 478 | optypes = readw_(cntlr.optype); |
| 479 | optypes = (optypes & 0xfffc) | (trans->type & 0x3); |
| 480 | writew_(optypes, cntlr.optype); |
| 481 | return 0; |
| 482 | } else { |
| 483 | /* The lock is on. See if what we need is on the menu. */ |
| 484 | uint8_t optype; |
| 485 | uint16_t opcode_index; |
| 486 | |
| 487 | read_reg(cntlr.opmenu, opmenu, sizeof(opmenu)); |
| 488 | for (opcode_index = 0; opcode_index < cntlr.menubytes; |
| 489 | opcode_index++) { |
| 490 | if (opmenu[opcode_index] == trans->opcode) |
| 491 | break; |
| 492 | } |
| 493 | |
| 494 | if (opcode_index == cntlr.menubytes) { |
| 495 | printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", |
| 496 | trans->opcode); |
| 497 | return -1; |
| 498 | } |
| 499 | |
| 500 | optypes = readw_(cntlr.optype); |
| 501 | optype = (optypes >> (opcode_index * 2)) & 0x3; |
| 502 | if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && |
| 503 | optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && |
| 504 | trans->bytesout >= 3) { |
| 505 | /* We guessed wrong earlier. Fix it up. */ |
| 506 | trans->type = optype; |
| 507 | } |
| 508 | if (optype != trans->type) { |
| 509 | printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n", |
| 510 | optype); |
| 511 | return -1; |
| 512 | } |
| 513 | return opcode_index; |
| 514 | } |
| 515 | } |
| 516 | |
| 517 | static int spi_setup_offset(spi_transaction *trans) |
| 518 | { |
| 519 | /* Separate the SPI address and data. */ |
| 520 | switch (trans->type) { |
| 521 | case SPI_OPCODE_TYPE_READ_NO_ADDRESS: |
| 522 | case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: |
| 523 | return 0; |
| 524 | case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: |
| 525 | case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: |
| 526 | trans->offset = ((uint32_t)trans->out[0] << 16) | |
| 527 | ((uint32_t)trans->out[1] << 8) | |
| 528 | ((uint32_t)trans->out[2] << 0); |
| 529 | spi_use_out(trans, 3); |
| 530 | return 1; |
| 531 | default: |
| 532 | printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", trans->type); |
| 533 | return -1; |
| 534 | } |
| 535 | } |
| 536 | |
| 537 | /* |
| 538 | * Wait for up to 60ms til status register bit(s) turn 1 (in case wait_til_set |
| 539 | * below is True) or 0. In case the wait was for the bit(s) to set - write |
| 540 | * those bits back, which would cause resetting them. |
| 541 | * |
| 542 | * Return the last read status value on success or -1 on failure. |
| 543 | */ |
| 544 | static int ich_status_poll(u16 bitmask, int wait_til_set) |
| 545 | { |
| 546 | int timeout = 6000; /* This will result in 60 ms */ |
| 547 | u16 status = 0; |
| 548 | |
| 549 | while (timeout--) { |
| 550 | status = readw_(cntlr.status); |
| 551 | if (wait_til_set ^ ((status & bitmask) == 0)) { |
| 552 | if (wait_til_set) |
| 553 | writew_((status & bitmask), cntlr.status); |
| 554 | return status; |
| 555 | } |
| 556 | udelay(10); |
| 557 | } |
| 558 | |
| 559 | printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, expected %x\n", |
| 560 | status, bitmask); |
| 561 | return -1; |
| 562 | } |
| 563 | |
| 564 | int spi_xfer(struct spi_slave *slave, const void *dout, |
| 565 | unsigned int bitsout, void *din, unsigned int bitsin) |
| 566 | { |
| 567 | uint16_t control; |
| 568 | int16_t opcode_index; |
| 569 | int with_address; |
| 570 | int status; |
| 571 | |
| 572 | spi_transaction trans = { |
| 573 | dout, bitsout / 8, |
| 574 | din, bitsin / 8, |
| 575 | 0xff, 0xff, 0 |
| 576 | }; |
| 577 | |
| 578 | /* There has to always at least be an opcode. */ |
| 579 | if (!bitsout || !dout) { |
| 580 | printk(BIOS_DEBUG, "ICH SPI: No opcode for transfer\n"); |
| 581 | return -1; |
| 582 | } |
| 583 | /* Make sure if we read something we have a place to put it. */ |
| 584 | if (bitsin != 0 && !din) { |
| 585 | printk(BIOS_DEBUG, "ICH SPI: Read but no target buffer\n"); |
| 586 | return -1; |
| 587 | } |
| 588 | /* Right now we don't support writing partial bytes. */ |
| 589 | if (bitsout % 8 || bitsin % 8) { |
| 590 | printk(BIOS_DEBUG, "ICH SPI: Accessing partial bytes not supported\n"); |
| 591 | return -1; |
| 592 | } |
| 593 | |
| 594 | if (ich_status_poll(SPIS_SCIP, 0) == -1) |
| 595 | return -1; |
| 596 | |
| 597 | writew_(SPIS_CDS | SPIS_FCERR, cntlr.status); |
| 598 | |
| 599 | spi_setup_type(&trans); |
| 600 | if ((opcode_index = spi_setup_opcode(&trans)) < 0) |
| 601 | return -1; |
| 602 | if ((with_address = spi_setup_offset(&trans)) < 0) |
| 603 | return -1; |
| 604 | |
| 605 | if (!ichspi_lock && trans.opcode == 0x06) { |
| 606 | /* |
| 607 | * Treat Write Enable as Atomic Pre-Op if possible |
| 608 | * in order to prevent the Management Engine from |
| 609 | * issuing a transaction between WREN and DATA. |
| 610 | */ |
| 611 | writew_(trans.opcode, cntlr.preop); |
| 612 | return 0; |
| 613 | } |
| 614 | |
| 615 | /* Preset control fields */ |
| 616 | control = SPIC_SCGO | ((opcode_index & 0x07) << 4); |
| 617 | |
| 618 | /* Issue atomic preop cycle if needed */ |
| 619 | if (readw_(cntlr.preop)) |
| 620 | control |= SPIC_ACS; |
| 621 | |
| 622 | if (!trans.bytesout && !trans.bytesin) { |
| 623 | /* |
| 624 | * This is a 'no data' command (like Write Enable), its |
| 625 | * bitesout size was 1, decremented to zero while executing |
| 626 | * spi_setup_opcode() above. Tell the chip to send the |
| 627 | * command. |
| 628 | */ |
| 629 | writew_(control, cntlr.control); |
| 630 | |
| 631 | /* wait for the result */ |
| 632 | status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); |
| 633 | if (status == -1) |
| 634 | return -1; |
| 635 | |
| 636 | if (status & SPIS_FCERR) { |
| 637 | printk(BIOS_DEBUG, "ICH SPI: Command transaction error\n"); |
| 638 | return -1; |
| 639 | } |
| 640 | |
| 641 | return 0; |
| 642 | } |
| 643 | |
| 644 | /* |
| 645 | * Check if this is a write command atempting to transfer more bytes |
| 646 | * than the controller can handle. Iterations for writes are not |
| 647 | * supported here because each SPI write command needs to be preceded |
| 648 | * and followed by other SPI commands, and this sequence is controlled |
| 649 | * by the SPI chip driver. |
| 650 | */ |
| 651 | if (trans.bytesout > cntlr.databytes) { |
| 652 | printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use" |
| 653 | " CONTROLLER_PAGE_LIMIT?\n"); |
| 654 | return -1; |
| 655 | } |
| 656 | |
| 657 | /* |
| 658 | * Read or write up to databytes bytes at a time until everything has |
| 659 | * been sent. |
| 660 | */ |
| 661 | while (trans.bytesout || trans.bytesin) { |
| 662 | uint32_t data_length; |
| 663 | |
| 664 | /* SPI addresses are 24 bit only */ |
| 665 | writel_(trans.offset & 0x00FFFFFF, cntlr.addr); |
| 666 | |
| 667 | if (trans.bytesout) |
| 668 | data_length = min(trans.bytesout, cntlr.databytes); |
| 669 | else |
| 670 | data_length = min(trans.bytesin, cntlr.databytes); |
| 671 | |
| 672 | /* Program data into FDATA0 to N */ |
| 673 | if (trans.bytesout) { |
| 674 | write_reg(trans.out, cntlr.data, data_length); |
| 675 | spi_use_out(&trans, data_length); |
| 676 | if (with_address) |
| 677 | trans.offset += data_length; |
| 678 | } |
| 679 | |
| 680 | /* Add proper control fields' values */ |
| 681 | control &= ~((cntlr.databytes - 1) << 8); |
| 682 | control |= SPIC_DS; |
| 683 | control |= (data_length - 1) << 8; |
| 684 | |
| 685 | /* write it */ |
| 686 | writew_(control, cntlr.control); |
| 687 | |
| 688 | /* Wait for Cycle Done Status or Flash Cycle Error. */ |
| 689 | status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); |
| 690 | if (status == -1) |
| 691 | return -1; |
| 692 | |
| 693 | if (status & SPIS_FCERR) { |
| 694 | printk(BIOS_DEBUG, "ICH SPI: Data transaction error\n"); |
| 695 | return -1; |
| 696 | } |
| 697 | |
| 698 | if (trans.bytesin) { |
| 699 | read_reg(cntlr.data, trans.in, data_length); |
| 700 | spi_use_in(&trans, data_length); |
| 701 | if (with_address) |
| 702 | trans.offset += data_length; |
| 703 | } |
| 704 | } |
| 705 | |
| 706 | /* Clear atomic preop now that xfer is done */ |
| 707 | writew_(0, cntlr.preop); |
| 708 | |
| 709 | return 0; |
| 710 | } |