commit 691c9f0dab96c1d5f4bbccb0991feb39e8986746
author Stefan Reinauer <reinauer@chromium.org> Wed May 23 11:18:35 2012 -0700
committer Stefan Reinauer <stefan.reinauer@coreboot.org> Wed May 30 00:53:11 2012 +0200
tree 82b3a46ed6c43c9ec5462b4c28f5781c3e05464d
parent 68b5da0e680b9066afa3bbff9e1ef99d2c7df720

Add support for Panther Point to SPI driver

Change-Id: I98b05d9e639eda880b6e8dc6398413d1f4f5e9c3
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1048
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

src/southbridge/intel/bd82x6x/spi.c

diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c
index 95fbfb9..ccc530d 100644
--- a/src/southbridge/intel/bd82x6x/spi.c
+++ b/src/southbridge/intel/bd82x6x/spi.c
@@ -286,11 +286,24 @@
 	free(slave);
 }
 
-static inline int spi_is_cougarpoint_lpc(uint16_t device_id)
+/*
+ * Check if this device ID matches one of supported Intel PCH devices.
+ *
+ * Return the ICH version if there is a match, or zero otherwise.
+ */
+static inline int get_ich_version(uint16_t device_id)
 {
-	return device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN &&
-		device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX;
-};
+	if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC)
+		return 7;
+
+	if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN &&
+	     device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) ||
+	    (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN &&
+	     device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX))
+		return 9;
+
+	return 0;
+}
 
 void spi_init(void)
 {
@@ -313,11 +326,9 @@
 		return;
 	}
 
-	if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC) {
-		ich_version = 7;
-	} else if (spi_is_cougarpoint_lpc(device_id)) {
-		ich_version = 9;
-	} else {
+	ich_version = get_ich_version(device_id);
+
+	if (!ich_version) {
 		printk(BIOS_DEBUG, "ICH SPI: No known ICH found.\n");
 		return;
 	}