Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2 | |
| 3 | #include <stdint.h> |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 4 | #include <console/console.h> |
| 5 | #include <arch/io.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 6 | #include <device/pci_ops.h> |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 7 | #include <device/pci_def.h> |
| 8 | #include <elog.h> |
| 9 | #include <cpu/x86/msr.h> |
| 10 | #include <cpu/intel/speedstep.h> |
| 11 | #include <cpu/intel/turbo.h> |
| 12 | #include <arch/cpu.h> |
| 13 | |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 14 | #include "ironlake.h" |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 15 | |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 16 | static void ironlake_setup_bars(void) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 17 | { |
| 18 | /* Setting up Southbridge. In the northbridge code. */ |
| 19 | printk(BIOS_DEBUG, "Setting up static southbridge registers..."); |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 20 | pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 21 | |
| 22 | pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); |
| 23 | /* Enable ACPI BAR */ |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 24 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 25 | |
| 26 | printk(BIOS_DEBUG, " done.\n"); |
| 27 | |
| 28 | printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); |
| 29 | /* No reset */ |
| 30 | RCBA32(GCS) = RCBA32(GCS) | (1 << 5); |
| 31 | /* halt timer */ |
| 32 | outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); |
| 33 | /* halt timer */ |
| 34 | outw(inw(DEFAULT_PMBASE | 0x60 | 0x06) | 2, |
| 35 | DEFAULT_PMBASE | 0x60 | 0x06); |
| 36 | printk(BIOS_DEBUG, " done.\n"); |
| 37 | |
| 38 | printk(BIOS_DEBUG, "Setting up static northbridge registers..."); |
| 39 | /* Set up all hardcoded northbridge BARs */ |
| 40 | pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); |
| 41 | pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, |
| 42 | (0LL + DEFAULT_EPBAR) >> 32); |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 43 | pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 44 | pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 45 | (0LL + (uintptr_t)DEFAULT_MCHBAR) >> 32); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 46 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 47 | pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 48 | pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 49 | (0LL + (uintptr_t)DEFAULT_DMIBAR) >> 32); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 50 | |
| 51 | /* Set C0000-FFFFF to access RAM on both reads and writes */ |
| 52 | pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(0), 0x30); |
| 53 | pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(1), 0x33); |
| 54 | pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(2), 0x33); |
| 55 | pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(3), 0x33); |
| 56 | pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(4), 0x33); |
| 57 | pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(5), 0x33); |
| 58 | pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(6), 0x33); |
| 59 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 60 | printk(BIOS_DEBUG, " done.\n"); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 61 | } |
| 62 | |
| 63 | static void early_cpu_init (void) |
| 64 | { |
| 65 | msr_t m; |
| 66 | |
| 67 | /* bit 0 = disable multicore, |
| 68 | bit 1 = disable quadcore, |
| 69 | bit 8 = disable hyperthreading. */ |
| 70 | pci_write_config32(PCI_DEV(0xff, 0x00, 0), 0x80, |
| 71 | (pci_read_config32(PCI_DEV(0xff, 0x0, 0x0), 0x80) & 0xfffffefc) | 0x10000); |
| 72 | |
| 73 | u8 reg8; |
| 74 | struct cpuid_result result; |
| 75 | result = cpuid_ext(0x6, 0x8b); |
| 76 | if (!(result.eax & 0x2)) { |
| 77 | m = rdmsr(MSR_FSB_CLOCK_VCC); |
| 78 | reg8 = ((m.lo & 0xff00) >> 8) + 1; |
Elyes HAOUAS | 4fe0cba | 2018-10-17 20:20:39 +0200 | [diff] [blame] | 79 | m = rdmsr(IA32_PERF_CTL); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 80 | m.lo = (m.lo & ~0xff) | reg8; |
| 81 | wrmsr(IA32_PERF_CTL, m); |
| 82 | |
Elyes HAOUAS | 419bfbc | 2018-10-01 08:47:51 +0200 | [diff] [blame] | 83 | m = rdmsr(IA32_MISC_ENABLE); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 84 | m.hi &= ~0x00000040; |
| 85 | m.lo |= 0x10000; |
| 86 | |
Elyes HAOUAS | 419bfbc | 2018-10-01 08:47:51 +0200 | [diff] [blame] | 87 | wrmsr(IA32_MISC_ENABLE, m); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 88 | } |
| 89 | |
| 90 | m = rdmsr(MSR_FSB_CLOCK_VCC); |
| 91 | reg8 = ((m.lo & 0xff00) >> 8) + 1; |
| 92 | |
Elyes HAOUAS | 4fe0cba | 2018-10-17 20:20:39 +0200 | [diff] [blame] | 93 | m = rdmsr(IA32_PERF_CTL); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 94 | m.lo = (m.lo & ~0xff) | reg8; |
| 95 | wrmsr(IA32_PERF_CTL, m); |
| 96 | |
Elyes HAOUAS | 419bfbc | 2018-10-01 08:47:51 +0200 | [diff] [blame] | 97 | m = rdmsr(IA32_MISC_ENABLE); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 98 | m.lo |= 0x10000; |
Elyes HAOUAS | 419bfbc | 2018-10-01 08:47:51 +0200 | [diff] [blame] | 99 | wrmsr(IA32_MISC_ENABLE, m); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 100 | } |
| 101 | |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 102 | void ironlake_early_initialization(int chipset_type) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 103 | { |
| 104 | u32 capid0_a; |
| 105 | u8 reg8; |
Kyösti Mälkki | 2cce24d | 2019-09-11 10:47:39 +0300 | [diff] [blame] | 106 | int s3_resume; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 107 | |
| 108 | /* Device ID Override Enable should be done very early */ |
| 109 | capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), 0xe4); |
| 110 | if (capid0_a & (1 << 10)) { |
| 111 | reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf3); |
| 112 | reg8 &= ~7; /* Clear 2:0 */ |
| 113 | |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 114 | if (chipset_type == IRONLAKE_MOBILE) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 115 | reg8 |= 1; /* Set bit 0 */ |
| 116 | |
| 117 | pci_write_config8(PCI_DEV(0, 0, 0), 0xf3, reg8); |
| 118 | } |
| 119 | |
| 120 | /* Setup all BARs required for early PCIe and raminit */ |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 121 | ironlake_setup_bars(); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 122 | |
Kyösti Mälkki | 2cce24d | 2019-09-11 10:47:39 +0300 | [diff] [blame] | 123 | s3_resume = (inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && |
| 124 | (((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3); |
| 125 | |
Kyösti Mälkki | 7f50afb | 2019-09-11 17:12:26 +0300 | [diff] [blame] | 126 | elog_boot_notify(s3_resume); |
Kyösti Mälkki | 2cce24d | 2019-09-11 10:47:39 +0300 | [diff] [blame] | 127 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 128 | /* Device Enable */ |
Patrick Rudolph | 847f12b | 2018-06-14 16:00:19 +0200 | [diff] [blame] | 129 | pci_write_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN, |
| 130 | DEVEN_IGD | DEVEN_PEG10 | DEVEN_HOST); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 131 | |
| 132 | early_cpu_init(); |
| 133 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 134 | pci_write_config32(PCI_DEV(0, 0x16, 0), 0x10, (uintptr_t)DEFAULT_HECIBAR); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 135 | pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_COMMAND, |
| 136 | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); |
Vladimir Serbinenko | bca9855 | 2014-01-09 11:13:18 +0100 | [diff] [blame] | 137 | |
| 138 | /* Magic for S3 resume. Must be done early. */ |
Kyösti Mälkki | 2cce24d | 2019-09-11 10:47:39 +0300 | [diff] [blame] | 139 | if (s3_resume) { |
Vladimir Serbinenko | bca9855 | 2014-01-09 11:13:18 +0100 | [diff] [blame] | 140 | MCHBAR32 (0x1e8) = (MCHBAR32(0x1e8) & ~1) | 6; |
| 141 | MCHBAR32 (0x1e8) = (MCHBAR32(0x1e8) & ~3) | 4; |
| 142 | } |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 143 | } |