Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation; version 2 of the License. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 13 | */ |
| 14 | |
| 15 | #include <console/console.h> |
| 16 | #include <arch/acpi.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 17 | #include <device/pci_ops.h> |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 18 | #include <stdint.h> |
| 19 | #include <delay.h> |
| 20 | #include <cpu/intel/model_2065x/model_2065x.h> |
| 21 | #include <cpu/x86/msr.h> |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 22 | #include <device/device.h> |
| 23 | #include <device/pci.h> |
| 24 | #include <device/pci_ids.h> |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 25 | #include "chip.h" |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 26 | #include "ironlake.h" |
Kyösti Mälkki | f091f4d | 2019-08-14 03:49:21 +0300 | [diff] [blame] | 27 | #include <cpu/intel/smm_reloc.h> |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 28 | |
| 29 | static int bridge_revision_id = -1; |
| 30 | |
| 31 | int bridge_silicon_revision(void) |
| 32 | { |
| 33 | if (bridge_revision_id < 0) { |
| 34 | uint8_t stepping = cpuid_eax(1) & 0xf; |
| 35 | uint8_t bridge_id = |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 36 | pci_read_config16(pcidev_on_root(0, 0), |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 37 | PCI_DEVICE_ID) & 0xf0; |
| 38 | bridge_revision_id = bridge_id | stepping; |
| 39 | } |
| 40 | return bridge_revision_id; |
| 41 | } |
| 42 | |
| 43 | /* Reserve everything between A segment and 1MB: |
| 44 | * |
| 45 | * 0xa0000 - 0xbffff: legacy VGA |
| 46 | * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel) |
| 47 | * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI |
| 48 | */ |
| 49 | static const int legacy_hole_base_k = 0xa0000 / 1024; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 50 | |
| 51 | static void add_fixed_resources(struct device *dev, int index) |
| 52 | { |
| 53 | struct resource *resource; |
| 54 | |
| 55 | /* 0xe0000000-0xf0000000 PCIe config. |
| 56 | 0xfed10000-0xfed14000 MCH |
| 57 | 0xfed17000-0xfed18000 HECI |
| 58 | 0xfed18000-0xfed19000 DMI |
| 59 | 0xfed19000-0xfed1a000 EPBAR |
| 60 | 0xfed1c000-0xfed20000 RCBA |
| 61 | 0xfed90000-0xfed94000 IOMMU |
| 62 | 0xff800000-0xffffffff ROM. */ |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 63 | |
| 64 | resource = new_resource(dev, index++); |
| 65 | resource->base = (resource_t) 0xfed00000; |
| 66 | resource->size = (resource_t) 0x00100000; |
| 67 | resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | |
| 68 | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; |
| 69 | |
| 70 | mmio_resource(dev, index++, legacy_hole_base_k, |
| 71 | (0xc0000 >> 10) - legacy_hole_base_k); |
| 72 | reserved_ram_resource(dev, index++, 0xc0000 >> 10, |
| 73 | (0x100000 - 0xc0000) >> 10); |
| 74 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 75 | #if CONFIG(CHROMEOS_RAMOOPS) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 76 | reserved_ram_resource(dev, index++, |
| 77 | CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, |
| 78 | CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); |
| 79 | #endif |
| 80 | } |
| 81 | |
Elyes HAOUAS | 706aabc | 2018-02-09 08:49:32 +0100 | [diff] [blame] | 82 | static void pci_domain_set_resources(struct device *dev) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 83 | { |
| 84 | assign_resources(dev->link_list); |
| 85 | } |
| 86 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 87 | #if CONFIG(HAVE_ACPI_TABLES) |
Patrick Rudolph | 5c3452b | 2018-05-15 11:37:26 +0200 | [diff] [blame] | 88 | static const char *northbridge_acpi_name(const struct device *dev) |
| 89 | { |
| 90 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 91 | return "PCI0"; |
| 92 | |
| 93 | if (dev->path.type != DEVICE_PATH_PCI || dev->bus->secondary != 0) |
| 94 | return NULL; |
| 95 | |
| 96 | switch (dev->path.pci.devfn) { |
| 97 | case PCI_DEVFN(0, 0): |
| 98 | return "MCHC"; |
| 99 | } |
| 100 | |
| 101 | return NULL; |
| 102 | } |
| 103 | #endif |
| 104 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 105 | static struct device_operations pci_domain_ops = { |
| 106 | .read_resources = pci_domain_read_resources, |
| 107 | .set_resources = pci_domain_set_resources, |
| 108 | .enable_resources = NULL, |
| 109 | .init = NULL, |
| 110 | .scan_bus = pci_domain_scan_bus, |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 111 | #if CONFIG(HAVE_ACPI_TABLES) |
Patrick Rudolph | 5c3452b | 2018-05-15 11:37:26 +0200 | [diff] [blame] | 112 | .acpi_name = northbridge_acpi_name, |
| 113 | #endif |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 114 | }; |
| 115 | |
Elyes HAOUAS | 706aabc | 2018-02-09 08:49:32 +0100 | [diff] [blame] | 116 | static void mc_read_resources(struct device *dev) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 117 | { |
| 118 | uint32_t tseg_base; |
| 119 | uint64_t TOUUD; |
| 120 | uint16_t reg16; |
| 121 | |
| 122 | pci_dev_read_resources(dev); |
| 123 | |
Kyösti Mälkki | e25b5ef | 2016-12-02 08:56:05 +0200 | [diff] [blame] | 124 | mmconf_resource(dev, 0x50); |
| 125 | |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 126 | tseg_base = pci_read_config32(pcidev_on_root(0, 0), TSEG); |
| 127 | TOUUD = pci_read_config16(pcidev_on_root(0, 0), |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 128 | D0F0_TOUUD); |
| 129 | |
| 130 | printk(BIOS_DEBUG, "ram_before_4g_top: 0x%x\n", tseg_base); |
Martin Roth | 468d02c | 2019-10-23 21:44:42 -0600 | [diff] [blame] | 131 | printk(BIOS_DEBUG, "TOUUD: 0x%x\n", (unsigned int)TOUUD); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 132 | |
| 133 | /* Report the memory regions */ |
| 134 | ram_resource(dev, 3, 0, 640); |
| 135 | ram_resource(dev, 4, 768, ((tseg_base >> 10) - 768)); |
| 136 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 137 | mmio_resource(dev, 5, tseg_base >> 10, CONFIG_SMM_TSEG_SIZE >> 10); |
| 138 | |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 139 | reg16 = pci_read_config16(pcidev_on_root(0, 0), D0F0_GGC); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 140 | const int uma_sizes_gtt[16] = |
| 141 | { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4, 42, 42, 42, 42 }; |
| 142 | /* Igd memory */ |
| 143 | const int uma_sizes_igd[16] = { |
| 144 | 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352, 256, 512 |
| 145 | }; |
| 146 | u32 igd_base, gtt_base; |
| 147 | int uma_size_igd, uma_size_gtt; |
| 148 | |
| 149 | uma_size_igd = uma_sizes_igd[(reg16 >> 4) & 0xF]; |
| 150 | uma_size_gtt = uma_sizes_gtt[(reg16 >> 8) & 0xF]; |
| 151 | |
| 152 | igd_base = |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 153 | pci_read_config32(pcidev_on_root(0, 0), D0F0_IGD_BASE); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 154 | gtt_base = |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 155 | pci_read_config32(pcidev_on_root(0, 0), D0F0_GTT_BASE); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 156 | mmio_resource(dev, 6, gtt_base >> 10, uma_size_gtt << 10); |
| 157 | mmio_resource(dev, 7, igd_base >> 10, uma_size_igd << 10); |
| 158 | |
| 159 | if (TOUUD > 4096) |
| 160 | ram_resource(dev, 8, (4096 << 10), ((TOUUD - 4096) << 10)); |
| 161 | |
| 162 | /* This memory is not DMA-capable. */ |
| 163 | if (TOUUD >= 8192 - 64) |
| 164 | bad_ram_resource(dev, 9, 0x1fc000000ULL >> 10, 0x004000000 >> 10); |
| 165 | |
| 166 | add_fixed_resources(dev, 10); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 167 | } |
| 168 | |
Elyes HAOUAS | 706aabc | 2018-02-09 08:49:32 +0100 | [diff] [blame] | 169 | static void mc_set_resources(struct device *dev) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 170 | { |
| 171 | /* And call the normal set_resources */ |
| 172 | pci_dev_set_resources(dev); |
| 173 | } |
| 174 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 175 | static void northbridge_dmi_init(struct device *dev) |
| 176 | { |
| 177 | u32 reg32; |
| 178 | |
| 179 | /* Clear error status bits */ |
| 180 | DMIBAR32(0x1c4) = 0xffffffff; |
| 181 | DMIBAR32(0x1d0) = 0xffffffff; |
| 182 | |
| 183 | /* Steps prior to DMI ASPM */ |
| 184 | if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { |
| 185 | reg32 = DMIBAR32(0x250); |
| 186 | reg32 &= ~((1 << 22) | (1 << 20)); |
| 187 | reg32 |= (1 << 21); |
| 188 | DMIBAR32(0x250) = reg32; |
| 189 | } |
| 190 | |
| 191 | reg32 = DMIBAR32(0x238); |
| 192 | reg32 |= (1 << 29); |
| 193 | DMIBAR32(0x238) = reg32; |
| 194 | |
| 195 | if (bridge_silicon_revision() >= SNB_STEP_D0) { |
| 196 | reg32 = DMIBAR32(0x1f8); |
| 197 | reg32 |= (1 << 16); |
| 198 | DMIBAR32(0x1f8) = reg32; |
| 199 | } else if (bridge_silicon_revision() >= SNB_STEP_D1) { |
| 200 | reg32 = DMIBAR32(0x1f8); |
| 201 | reg32 &= ~(1 << 26); |
| 202 | reg32 |= (1 << 16); |
| 203 | DMIBAR32(0x1f8) = reg32; |
| 204 | |
| 205 | reg32 = DMIBAR32(0x1fc); |
| 206 | reg32 |= (1 << 12) | (1 << 23); |
| 207 | DMIBAR32(0x1fc) = reg32; |
| 208 | } |
| 209 | |
| 210 | /* Enable ASPM on SNB link, should happen before PCH link */ |
| 211 | if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { |
| 212 | reg32 = DMIBAR32(0xd04); |
| 213 | reg32 |= (1 << 4); |
| 214 | DMIBAR32(0xd04) = reg32; |
| 215 | } |
| 216 | |
| 217 | reg32 = DMIBAR32(0x88); |
| 218 | reg32 |= (1 << 1) | (1 << 0); |
| 219 | DMIBAR32(0x88) = reg32; |
| 220 | } |
| 221 | |
| 222 | static void northbridge_init(struct device *dev) |
| 223 | { |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 224 | northbridge_dmi_init(dev); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 225 | } |
| 226 | |
Arthur Heymans | 28bca05 | 2019-10-01 21:20:33 +0200 | [diff] [blame] | 227 | /* Disable unused PEG devices based on devicetree before PCI enumeration */ |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 228 | static void ironlake_init(void *const chip_info) |
Arthur Heymans | 28bca05 | 2019-10-01 21:20:33 +0200 | [diff] [blame] | 229 | { |
| 230 | u32 deven_mask = UINT32_MAX; |
| 231 | const struct device *dev; |
| 232 | |
| 233 | dev = pcidev_on_root(1, 0); |
| 234 | if (!dev || !dev->enabled) { |
| 235 | printk(BIOS_DEBUG, "Disabling PEG10.\n"); |
| 236 | deven_mask &= ~DEVEN_PEG10; |
| 237 | } |
| 238 | dev = pcidev_on_root(2, 0); |
| 239 | if (!dev || !dev->enabled) { |
| 240 | printk(BIOS_DEBUG, "Disabling IGD.\n"); |
| 241 | deven_mask &= ~DEVEN_IGD; |
| 242 | } |
| 243 | const struct device *const d0f0 = pcidev_on_root(0, 0); |
| 244 | if (d0f0) |
| 245 | pci_update_config32(d0f0, D0F0_DEVEN, deven_mask, 0); |
| 246 | |
| 247 | } |
| 248 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 249 | static struct pci_operations intel_pci_ops = { |
Subrata Banik | 4a0f071 | 2019-03-20 14:29:47 +0530 | [diff] [blame] | 250 | .set_subsystem = pci_dev_set_subsystem, |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 251 | }; |
| 252 | |
| 253 | static struct device_operations mc_ops = { |
| 254 | .read_resources = mc_read_resources, |
| 255 | .set_resources = mc_set_resources, |
| 256 | .enable_resources = pci_dev_enable_resources, |
| 257 | .init = northbridge_init, |
Vladimir Serbinenko | 0a66991 | 2014-10-05 14:34:17 +0200 | [diff] [blame] | 258 | .acpi_fill_ssdt_generator = generate_cpu_entries, |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 259 | .scan_bus = 0, |
| 260 | .ops_pci = &intel_pci_ops, |
| 261 | }; |
| 262 | |
Angel Pons | 31b7ee4 | 2020-02-17 14:04:28 +0100 | [diff] [blame] | 263 | static const struct pci_driver mc_driver_ard __pci_driver = { |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 264 | .ops = &mc_ops, |
| 265 | .vendor = PCI_VENDOR_ID_INTEL, |
Angel Pons | 31b7ee4 | 2020-02-17 14:04:28 +0100 | [diff] [blame] | 266 | .device = 0x0044, /* Arrandale DRAM controller */ |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 267 | }; |
| 268 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 269 | static struct device_operations cpu_bus_ops = { |
Edward O'Callaghan | 9f74462 | 2014-10-31 08:12:34 +1100 | [diff] [blame] | 270 | .read_resources = DEVICE_NOOP, |
| 271 | .set_resources = DEVICE_NOOP, |
| 272 | .enable_resources = DEVICE_NOOP, |
Kyösti Mälkki | b3267e0 | 2019-08-13 16:44:04 +0300 | [diff] [blame] | 273 | .init = mp_cpu_bus_init, |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 274 | .scan_bus = 0, |
| 275 | }; |
| 276 | |
Elyes HAOUAS | 706aabc | 2018-02-09 08:49:32 +0100 | [diff] [blame] | 277 | static void enable_dev(struct device *dev) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 278 | { |
| 279 | /* Set the operations if it is a special bus type */ |
| 280 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
| 281 | dev->ops = &pci_domain_ops; |
| 282 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
| 283 | dev->ops = &cpu_bus_ops; |
| 284 | } |
| 285 | } |
| 286 | |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 287 | struct chip_operations northbridge_intel_ironlake_ops = { |
Angel Pons | 31b7ee4 | 2020-02-17 14:04:28 +0100 | [diff] [blame] | 288 | CHIP_NAME("Intel i7 (Arrandale) integrated Northbridge") |
Arthur Heymans | 28bca05 | 2019-10-01 21:20:33 +0200 | [diff] [blame] | 289 | .enable_dev = enable_dev, |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 290 | .init = ironlake_init, |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 291 | }; |