Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * Copyright (C) 2013 Vladimir Serbinenko |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #include <console/console.h> |
| 19 | #include <arch/acpi.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 20 | #include <device/pci_ops.h> |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 21 | #include <stdint.h> |
| 22 | #include <delay.h> |
| 23 | #include <cpu/intel/model_2065x/model_2065x.h> |
| 24 | #include <cpu/x86/msr.h> |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 25 | #include <device/device.h> |
| 26 | #include <device/pci.h> |
| 27 | #include <device/pci_ids.h> |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 28 | #include <stdlib.h> |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 29 | #include <cpu/cpu.h> |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 30 | #include "chip.h" |
| 31 | #include "nehalem.h" |
Vladimir Serbinenko | 0f9aa1c | 2015-05-29 16:52:50 +0200 | [diff] [blame] | 32 | #include <cpu/intel/smm/gen1/smi.h> |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 33 | |
| 34 | static int bridge_revision_id = -1; |
| 35 | |
| 36 | int bridge_silicon_revision(void) |
| 37 | { |
| 38 | if (bridge_revision_id < 0) { |
| 39 | uint8_t stepping = cpuid_eax(1) & 0xf; |
| 40 | uint8_t bridge_id = |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 41 | pci_read_config16(pcidev_on_root(0, 0), |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 42 | PCI_DEVICE_ID) & 0xf0; |
| 43 | bridge_revision_id = bridge_id | stepping; |
| 44 | } |
| 45 | return bridge_revision_id; |
| 46 | } |
| 47 | |
| 48 | /* Reserve everything between A segment and 1MB: |
| 49 | * |
| 50 | * 0xa0000 - 0xbffff: legacy VGA |
| 51 | * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel) |
| 52 | * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI |
| 53 | */ |
| 54 | static const int legacy_hole_base_k = 0xa0000 / 1024; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 55 | |
| 56 | static void add_fixed_resources(struct device *dev, int index) |
| 57 | { |
| 58 | struct resource *resource; |
| 59 | |
| 60 | /* 0xe0000000-0xf0000000 PCIe config. |
| 61 | 0xfed10000-0xfed14000 MCH |
| 62 | 0xfed17000-0xfed18000 HECI |
| 63 | 0xfed18000-0xfed19000 DMI |
| 64 | 0xfed19000-0xfed1a000 EPBAR |
| 65 | 0xfed1c000-0xfed20000 RCBA |
| 66 | 0xfed90000-0xfed94000 IOMMU |
| 67 | 0xff800000-0xffffffff ROM. */ |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 68 | |
| 69 | resource = new_resource(dev, index++); |
| 70 | resource->base = (resource_t) 0xfed00000; |
| 71 | resource->size = (resource_t) 0x00100000; |
| 72 | resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | |
| 73 | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; |
| 74 | |
| 75 | mmio_resource(dev, index++, legacy_hole_base_k, |
| 76 | (0xc0000 >> 10) - legacy_hole_base_k); |
| 77 | reserved_ram_resource(dev, index++, 0xc0000 >> 10, |
| 78 | (0x100000 - 0xc0000) >> 10); |
| 79 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 80 | #if CONFIG(CHROMEOS_RAMOOPS) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 81 | reserved_ram_resource(dev, index++, |
| 82 | CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, |
| 83 | CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); |
| 84 | #endif |
| 85 | } |
| 86 | |
Elyes HAOUAS | 706aabc | 2018-02-09 08:49:32 +0100 | [diff] [blame] | 87 | static void pci_domain_set_resources(struct device *dev) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 88 | { |
| 89 | assign_resources(dev->link_list); |
| 90 | } |
| 91 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 92 | #if CONFIG(HAVE_ACPI_TABLES) |
Patrick Rudolph | 5c3452b | 2018-05-15 11:37:26 +0200 | [diff] [blame] | 93 | static const char *northbridge_acpi_name(const struct device *dev) |
| 94 | { |
| 95 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 96 | return "PCI0"; |
| 97 | |
| 98 | if (dev->path.type != DEVICE_PATH_PCI || dev->bus->secondary != 0) |
| 99 | return NULL; |
| 100 | |
| 101 | switch (dev->path.pci.devfn) { |
| 102 | case PCI_DEVFN(0, 0): |
| 103 | return "MCHC"; |
| 104 | } |
| 105 | |
| 106 | return NULL; |
| 107 | } |
| 108 | #endif |
| 109 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 110 | static struct device_operations pci_domain_ops = { |
| 111 | .read_resources = pci_domain_read_resources, |
| 112 | .set_resources = pci_domain_set_resources, |
| 113 | .enable_resources = NULL, |
| 114 | .init = NULL, |
| 115 | .scan_bus = pci_domain_scan_bus, |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 116 | #if CONFIG(HAVE_ACPI_TABLES) |
Patrick Rudolph | 5c3452b | 2018-05-15 11:37:26 +0200 | [diff] [blame] | 117 | .acpi_name = northbridge_acpi_name, |
| 118 | #endif |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 119 | }; |
| 120 | |
Elyes HAOUAS | 706aabc | 2018-02-09 08:49:32 +0100 | [diff] [blame] | 121 | static void mc_read_resources(struct device *dev) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 122 | { |
| 123 | uint32_t tseg_base; |
| 124 | uint64_t TOUUD; |
| 125 | uint16_t reg16; |
| 126 | |
| 127 | pci_dev_read_resources(dev); |
| 128 | |
Kyösti Mälkki | e25b5ef | 2016-12-02 08:56:05 +0200 | [diff] [blame] | 129 | mmconf_resource(dev, 0x50); |
| 130 | |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 131 | tseg_base = pci_read_config32(pcidev_on_root(0, 0), TSEG); |
| 132 | TOUUD = pci_read_config16(pcidev_on_root(0, 0), |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 133 | D0F0_TOUUD); |
| 134 | |
| 135 | printk(BIOS_DEBUG, "ram_before_4g_top: 0x%x\n", tseg_base); |
| 136 | printk(BIOS_DEBUG, "TOUUD: 0x%x\n", (unsigned)TOUUD); |
| 137 | |
| 138 | /* Report the memory regions */ |
| 139 | ram_resource(dev, 3, 0, 640); |
| 140 | ram_resource(dev, 4, 768, ((tseg_base >> 10) - 768)); |
| 141 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 142 | mmio_resource(dev, 5, tseg_base >> 10, CONFIG_SMM_TSEG_SIZE >> 10); |
| 143 | |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 144 | reg16 = pci_read_config16(pcidev_on_root(0, 0), D0F0_GGC); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 145 | const int uma_sizes_gtt[16] = |
| 146 | { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4, 42, 42, 42, 42 }; |
| 147 | /* Igd memory */ |
| 148 | const int uma_sizes_igd[16] = { |
| 149 | 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352, 256, 512 |
| 150 | }; |
| 151 | u32 igd_base, gtt_base; |
| 152 | int uma_size_igd, uma_size_gtt; |
| 153 | |
| 154 | uma_size_igd = uma_sizes_igd[(reg16 >> 4) & 0xF]; |
| 155 | uma_size_gtt = uma_sizes_gtt[(reg16 >> 8) & 0xF]; |
| 156 | |
| 157 | igd_base = |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 158 | pci_read_config32(pcidev_on_root(0, 0), D0F0_IGD_BASE); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 159 | gtt_base = |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 160 | pci_read_config32(pcidev_on_root(0, 0), D0F0_GTT_BASE); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 161 | mmio_resource(dev, 6, gtt_base >> 10, uma_size_gtt << 10); |
| 162 | mmio_resource(dev, 7, igd_base >> 10, uma_size_igd << 10); |
| 163 | |
| 164 | if (TOUUD > 4096) |
| 165 | ram_resource(dev, 8, (4096 << 10), ((TOUUD - 4096) << 10)); |
| 166 | |
| 167 | /* This memory is not DMA-capable. */ |
| 168 | if (TOUUD >= 8192 - 64) |
| 169 | bad_ram_resource(dev, 9, 0x1fc000000ULL >> 10, 0x004000000 >> 10); |
| 170 | |
| 171 | add_fixed_resources(dev, 10); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 172 | } |
| 173 | |
Nico Huber | 6f8b7df | 2016-10-08 18:42:46 +0200 | [diff] [blame] | 174 | u32 northbridge_get_tseg_base(void) |
Vladimir Serbinenko | 0f9aa1c | 2015-05-29 16:52:50 +0200 | [diff] [blame] | 175 | { |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 176 | struct device *dev = pcidev_on_root(0, 0); |
Vladimir Serbinenko | 0f9aa1c | 2015-05-29 16:52:50 +0200 | [diff] [blame] | 177 | |
Nico Huber | 6f8b7df | 2016-10-08 18:42:46 +0200 | [diff] [blame] | 178 | return pci_read_config32(dev, TSEG) & ~1; |
Vladimir Serbinenko | 0f9aa1c | 2015-05-29 16:52:50 +0200 | [diff] [blame] | 179 | } |
| 180 | |
Arthur Heymans | aade90e | 2018-01-25 00:33:45 +0100 | [diff] [blame] | 181 | u32 northbridge_get_tseg_size(void) |
| 182 | { |
| 183 | return CONFIG_SMM_TSEG_SIZE; |
| 184 | } |
| 185 | |
Elyes HAOUAS | 706aabc | 2018-02-09 08:49:32 +0100 | [diff] [blame] | 186 | static void mc_set_resources(struct device *dev) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 187 | { |
| 188 | /* And call the normal set_resources */ |
| 189 | pci_dev_set_resources(dev); |
| 190 | } |
| 191 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 192 | static void northbridge_dmi_init(struct device *dev) |
| 193 | { |
| 194 | u32 reg32; |
| 195 | |
| 196 | /* Clear error status bits */ |
| 197 | DMIBAR32(0x1c4) = 0xffffffff; |
| 198 | DMIBAR32(0x1d0) = 0xffffffff; |
| 199 | |
| 200 | /* Steps prior to DMI ASPM */ |
| 201 | if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { |
| 202 | reg32 = DMIBAR32(0x250); |
| 203 | reg32 &= ~((1 << 22) | (1 << 20)); |
| 204 | reg32 |= (1 << 21); |
| 205 | DMIBAR32(0x250) = reg32; |
| 206 | } |
| 207 | |
| 208 | reg32 = DMIBAR32(0x238); |
| 209 | reg32 |= (1 << 29); |
| 210 | DMIBAR32(0x238) = reg32; |
| 211 | |
| 212 | if (bridge_silicon_revision() >= SNB_STEP_D0) { |
| 213 | reg32 = DMIBAR32(0x1f8); |
| 214 | reg32 |= (1 << 16); |
| 215 | DMIBAR32(0x1f8) = reg32; |
| 216 | } else if (bridge_silicon_revision() >= SNB_STEP_D1) { |
| 217 | reg32 = DMIBAR32(0x1f8); |
| 218 | reg32 &= ~(1 << 26); |
| 219 | reg32 |= (1 << 16); |
| 220 | DMIBAR32(0x1f8) = reg32; |
| 221 | |
| 222 | reg32 = DMIBAR32(0x1fc); |
| 223 | reg32 |= (1 << 12) | (1 << 23); |
| 224 | DMIBAR32(0x1fc) = reg32; |
| 225 | } |
| 226 | |
| 227 | /* Enable ASPM on SNB link, should happen before PCH link */ |
| 228 | if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { |
| 229 | reg32 = DMIBAR32(0xd04); |
| 230 | reg32 |= (1 << 4); |
| 231 | DMIBAR32(0xd04) = reg32; |
| 232 | } |
| 233 | |
| 234 | reg32 = DMIBAR32(0x88); |
| 235 | reg32 |= (1 << 1) | (1 << 0); |
| 236 | DMIBAR32(0x88) = reg32; |
| 237 | } |
| 238 | |
| 239 | static void northbridge_init(struct device *dev) |
| 240 | { |
| 241 | u8 bios_reset_cpl; |
| 242 | u32 bridge_type; |
| 243 | |
| 244 | northbridge_dmi_init(dev); |
| 245 | |
| 246 | bridge_type = MCHBAR32(0x5f10); |
| 247 | bridge_type &= ~0xff; |
| 248 | |
| 249 | if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { |
| 250 | /* Enable Power Aware Interrupt Routing */ |
| 251 | u8 pair = MCHBAR8(0x5418); |
| 252 | pair &= ~0xf; /* Clear 3:0 */ |
| 253 | pair |= 0x4; /* Fixed Priority */ |
| 254 | MCHBAR8(0x5418) = pair; |
| 255 | |
| 256 | /* 30h for IvyBridge */ |
| 257 | bridge_type |= 0x30; |
| 258 | } else { |
| 259 | /* 20h for Sandybridge */ |
| 260 | bridge_type |= 0x20; |
| 261 | } |
| 262 | MCHBAR32(0x5f10) = bridge_type; |
| 263 | |
| 264 | /* |
| 265 | * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU |
| 266 | * that BIOS has initialized memory and power management |
| 267 | */ |
| 268 | bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL); |
| 269 | bios_reset_cpl |= 1; |
| 270 | MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl; |
| 271 | printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); |
| 272 | |
| 273 | /* Configure turbo power limits 1ms after reset complete bit */ |
| 274 | mdelay(1); |
| 275 | #ifdef DISABLED |
| 276 | set_power_limits(28); |
| 277 | |
| 278 | /* |
| 279 | * CPUs with configurable TDP also need power limits set |
| 280 | * in MCHBAR. Use same values from MSR_PKG_POWER_LIMIT. |
| 281 | */ |
| 282 | if (cpu_config_tdp_levels()) { |
| 283 | msr_t msr = rdmsr(MSR_PKG_POWER_LIMIT); |
| 284 | MCHBAR32(0x59A0) = msr.lo; |
| 285 | MCHBAR32(0x59A4) = msr.hi; |
| 286 | } |
| 287 | #endif |
| 288 | /* Set here before graphics PM init */ |
| 289 | MCHBAR32(0x5500) = 0x00100001; |
| 290 | } |
| 291 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 292 | static struct pci_operations intel_pci_ops = { |
Subrata Banik | 4a0f071 | 2019-03-20 14:29:47 +0530 | [diff] [blame^] | 293 | .set_subsystem = pci_dev_set_subsystem, |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 294 | }; |
| 295 | |
| 296 | static struct device_operations mc_ops = { |
| 297 | .read_resources = mc_read_resources, |
| 298 | .set_resources = mc_set_resources, |
| 299 | .enable_resources = pci_dev_enable_resources, |
| 300 | .init = northbridge_init, |
Vladimir Serbinenko | 0a66991 | 2014-10-05 14:34:17 +0200 | [diff] [blame] | 301 | .acpi_fill_ssdt_generator = generate_cpu_entries, |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 302 | .scan_bus = 0, |
| 303 | .ops_pci = &intel_pci_ops, |
| 304 | }; |
| 305 | |
| 306 | static const struct pci_driver mc_driver_44 __pci_driver = { |
| 307 | .ops = &mc_ops, |
| 308 | .vendor = PCI_VENDOR_ID_INTEL, |
| 309 | .device = 0x0044, /* Nehalem */ |
| 310 | }; |
| 311 | |
Elyes HAOUAS | 706aabc | 2018-02-09 08:49:32 +0100 | [diff] [blame] | 312 | static void cpu_bus_init(struct device *dev) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 313 | { |
| 314 | initialize_cpus(dev->link_list); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 315 | } |
| 316 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 317 | static struct device_operations cpu_bus_ops = { |
Edward O'Callaghan | 9f74462 | 2014-10-31 08:12:34 +1100 | [diff] [blame] | 318 | .read_resources = DEVICE_NOOP, |
| 319 | .set_resources = DEVICE_NOOP, |
| 320 | .enable_resources = DEVICE_NOOP, |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 321 | .init = cpu_bus_init, |
| 322 | .scan_bus = 0, |
| 323 | }; |
| 324 | |
Elyes HAOUAS | 706aabc | 2018-02-09 08:49:32 +0100 | [diff] [blame] | 325 | static void enable_dev(struct device *dev) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 326 | { |
| 327 | /* Set the operations if it is a special bus type */ |
| 328 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
| 329 | dev->ops = &pci_domain_ops; |
| 330 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
| 331 | dev->ops = &cpu_bus_ops; |
| 332 | } |
| 333 | } |
| 334 | |
| 335 | struct chip_operations northbridge_intel_nehalem_ops = { |
| 336 | CHIP_NAME("Intel i7 (Nehalem) integrated Northbridge") |
| 337 | .enable_dev = enable_dev, |
| 338 | }; |