Lance Zhao | f51b127 | 2015-11-09 17:06:34 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2016 Intel Corp. |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 5 | * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.) |
Lance Zhao | f51b127 | 2015-11-09 17:06:34 -0800 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
Martin Roth | ebabfad | 2016-04-10 11:09:16 -0600 | [diff] [blame] | 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Lance Zhao | f51b127 | 2015-11-09 17:06:34 -0800 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #include <arch/acpi.h> |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 19 | #include <arch/acpigen.h> |
Lance Zhao | 2fc82d6 | 2015-11-16 18:33:21 -0800 | [diff] [blame] | 20 | #include <arch/ioapic.h> |
| 21 | #include <arch/smp/mpspec.h> |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 22 | #include <cbmem.h> |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 23 | #include <cpu/x86/smm.h> |
Aaron Durbin | 1ee6f0b | 2016-06-10 15:50:34 -0500 | [diff] [blame] | 24 | #include <cpu/cpu.h> |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 25 | #include <soc/acpi.h> |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 26 | #include <soc/intel/common/acpi.h> |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 27 | #include <soc/iomap.h> |
| 28 | #include <soc/pm.h> |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 29 | #include <soc/nvs.h> |
Shaunak Saha | cd9e1e4 | 2016-07-12 01:22:33 -0700 | [diff] [blame] | 30 | #include <soc/pci_devs.h> |
Aaron Durbin | 9e81540 | 2016-09-13 12:31:57 -0500 | [diff] [blame] | 31 | #include <string.h> |
Vaibhav Shankar | ef8deaf | 2016-08-23 17:56:17 -0700 | [diff] [blame] | 32 | #include <soc/gpio.h> |
Shaunak Saha | cd9e1e4 | 2016-07-12 01:22:33 -0700 | [diff] [blame] | 33 | #include "chip.h" |
Lance Zhao | f51b127 | 2015-11-09 17:06:34 -0800 | [diff] [blame] | 34 | |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 35 | #define CSTATE_RES(address_space, width, offset, address) \ |
| 36 | { \ |
| 37 | .space_id = address_space, \ |
| 38 | .bit_width = width, \ |
| 39 | .bit_offset = offset, \ |
| 40 | .addrl = address, \ |
| 41 | } |
| 42 | |
Lance Zhao | f51b127 | 2015-11-09 17:06:34 -0800 | [diff] [blame] | 43 | unsigned long acpi_fill_mcfg(unsigned long current) |
| 44 | { |
Lance Zhao | 2c34e31 | 2015-11-16 18:13:23 -0800 | [diff] [blame] | 45 | /* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */ |
| 46 | current += acpi_create_mcfg_mmconfig((void *) current, |
| 47 | CONFIG_MMCONF_BASE_ADDRESS, 0, 0, |
| 48 | 255); |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 49 | return current; |
Lance Zhao | f51b127 | 2015-11-09 17:06:34 -0800 | [diff] [blame] | 50 | } |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 51 | |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 52 | static int acpi_sci_irq(void) |
| 53 | { |
| 54 | int sci_irq = 9; |
| 55 | return sci_irq; |
| 56 | } |
| 57 | |
Lance Zhao | 2fc82d6 | 2015-11-16 18:33:21 -0800 | [diff] [blame] | 58 | static unsigned long acpi_madt_irq_overrides(unsigned long current) |
| 59 | { |
| 60 | int sci = acpi_sci_irq(); |
| 61 | uint16_t flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW;; |
| 62 | |
| 63 | /* INT_SRC_OVR */ |
| 64 | current += acpi_create_madt_irqoverride((void *)current, 0, 0, 2, 0); |
| 65 | |
| 66 | /* SCI */ |
| 67 | current += acpi_create_madt_irqoverride((void *)current, 0, sci, sci, flags); |
| 68 | |
| 69 | return current; |
| 70 | } |
| 71 | |
| 72 | unsigned long acpi_fill_madt(unsigned long current) |
| 73 | { |
| 74 | /* Local APICs */ |
| 75 | current = acpi_create_madt_lapics(current); |
| 76 | |
| 77 | /* IOAPIC */ |
| 78 | current += acpi_create_madt_ioapic((void *) current, |
| 79 | 2, IO_APIC_ADDR, 0); |
| 80 | |
| 81 | return acpi_madt_irq_overrides(current); |
| 82 | } |
| 83 | |
Lee Leahy | 68571c1 | 2017-03-09 09:26:05 -0800 | [diff] [blame^] | 84 | void acpi_fill_fadt(acpi_fadt_t *fadt) |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 85 | { |
| 86 | const uint16_t pmbase = ACPI_PMIO_BASE; |
| 87 | |
Aaron Durbin | c3ee3f6 | 2016-05-11 10:35:49 -0500 | [diff] [blame] | 88 | /* Use ACPI 5.0 revision. */ |
| 89 | fadt->header.revision = ACPI_FADT_REV_ACPI_5_0; |
| 90 | |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 91 | fadt->sci_int = acpi_sci_irq(); |
Hannah Williams | 6516422 | 2016-06-24 14:13:45 -0700 | [diff] [blame] | 92 | fadt->smi_cmd = APM_CNT; |
| 93 | fadt->acpi_enable = APM_CNT_ACPI_ENABLE; |
| 94 | fadt->acpi_disable = APM_CNT_ACPI_DISABLE; |
Lance Zhao | e904c7c | 2015-11-10 19:00:18 -0800 | [diff] [blame] | 95 | |
| 96 | fadt->pm1a_evt_blk = pmbase + PM1_STS; |
| 97 | fadt->pm1a_cnt_blk = pmbase + PM1_CNT; |
| 98 | fadt->pm_tmr_blk = pmbase + PM1_TMR; |
| 99 | fadt->gpe0_blk = pmbase + GPE0_STS(0); |
| 100 | |
| 101 | fadt->pm1_evt_len = 4; |
| 102 | fadt->pm1_cnt_len = 2; |
| 103 | fadt->pm_tmr_len = 4; |
| 104 | /* There are 4 GPE0 STS/EN pairs each 32 bits wide. */ |
| 105 | fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); |
| 106 | fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; |
| 107 | fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; |
| 108 | fadt->flush_size = 0x400; /* twice of cache size*/ |
| 109 | fadt->flush_stride = 0x10; /* Cache line width */ |
| 110 | fadt->duty_offset = 1; |
| 111 | fadt->duty_width = 3; |
| 112 | fadt->day_alrm = 0xd; |
| 113 | fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; |
| 114 | |
| 115 | fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | |
| 116 | ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | |
| 117 | ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | |
| 118 | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; |
| 119 | |
| 120 | fadt->reset_reg.space_id = 1; |
| 121 | fadt->reset_reg.bit_width = 8; |
| 122 | fadt->reset_reg.addrl = 0xcf9; |
| 123 | fadt->reset_value = 6; |
| 124 | |
| 125 | fadt->x_pm1a_evt_blk.space_id = 1; |
| 126 | fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; |
| 127 | fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; |
| 128 | |
| 129 | fadt->x_pm1b_evt_blk.space_id = 1; |
| 130 | |
| 131 | fadt->x_pm1a_cnt_blk.space_id = 1; |
| 132 | fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; |
| 133 | fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; |
| 134 | |
| 135 | fadt->x_pm1b_cnt_blk.space_id = 1; |
| 136 | |
| 137 | fadt->x_pm_tmr_blk.space_id = 1; |
| 138 | fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; |
| 139 | fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; |
| 140 | |
| 141 | fadt->x_gpe1_blk.space_id = 1; |
Lance Zhao | f51b127 | 2015-11-09 17:06:34 -0800 | [diff] [blame] | 142 | } |
Zhao, Lijian | 30461a9 | 2015-12-01 09:14:20 -0800 | [diff] [blame] | 143 | |
| 144 | unsigned long southbridge_write_acpi_tables(device_t device, |
| 145 | unsigned long current, |
| 146 | struct acpi_rsdp *rsdp) |
| 147 | { |
| 148 | return acpi_write_hpet(device, current, rsdp); |
| 149 | } |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 150 | |
| 151 | static void acpi_create_gnvs(struct global_nvs_t *gnvs) |
| 152 | { |
Shaunak Saha | cd9e1e4 | 2016-07-12 01:22:33 -0700 | [diff] [blame] | 153 | struct soc_intel_apollolake_config *cfg; |
| 154 | struct device *dev = NB_DEV_ROOT; |
| 155 | |
Aaron Durbin | 9e81540 | 2016-09-13 12:31:57 -0500 | [diff] [blame] | 156 | /* Clear out GNVS. */ |
| 157 | memset(gnvs, 0, sizeof(*gnvs)); |
Shaunak Saha | cd9e1e4 | 2016-07-12 01:22:33 -0700 | [diff] [blame] | 158 | |
Furquan Shaikh | d01f5a0 | 2016-06-13 22:23:49 -0700 | [diff] [blame] | 159 | if (IS_ENABLED(CONFIG_CONSOLE_CBMEM)) |
| 160 | gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE); |
| 161 | |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 162 | if (IS_ENABLED(CONFIG_CHROMEOS)) { |
| 163 | /* Initialize Verified Boot data */ |
| 164 | chromeos_init_vboot(&gnvs->chromeos); |
| 165 | gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; |
| 166 | } |
Shaunak Saha | cd9e1e4 | 2016-07-12 01:22:33 -0700 | [diff] [blame] | 167 | |
Shaunak Saha | 60b4618 | 2016-08-02 17:25:13 -0700 | [diff] [blame] | 168 | /* Set unknown wake source */ |
| 169 | gnvs->pm1i = ~0ULL; |
Aaron Durbin | 9e81540 | 2016-09-13 12:31:57 -0500 | [diff] [blame] | 170 | |
Duncan Laurie | 1d359b5 | 2016-09-21 18:30:44 -0700 | [diff] [blame] | 171 | /* CPU core count */ |
| 172 | gnvs->pcnt = dev_count_cpu(); |
| 173 | |
Aaron Durbin | 9e81540 | 2016-09-13 12:31:57 -0500 | [diff] [blame] | 174 | if (!dev || !dev->chip_info) { |
| 175 | printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); |
| 176 | return; |
| 177 | } |
| 178 | cfg = dev->chip_info; |
| 179 | |
| 180 | /* Enable DPTF based on mainboard configuration */ |
| 181 | gnvs->dpte = cfg->dptf_enable; |
Vaibhav Shankar | ef8deaf | 2016-08-23 17:56:17 -0700 | [diff] [blame] | 182 | |
| 183 | /* Assign address of PERST_0 if GPIO is defined in devicetree */ |
| 184 | if (cfg->prt0_gpio != GPIO_PRT0_UDEF) |
| 185 | gnvs->prt0 = (uintptr_t)gpio_dwx_address(cfg->prt0_gpio); |
Venkateswarlu Vinjamuri | 6dd7b40 | 2017-02-24 15:37:30 -0800 | [diff] [blame] | 186 | |
| 187 | /* Assign sdcard cd address if GPIO is defined in devicetree */ |
| 188 | if (cfg->sdcard_cd_gpio) |
| 189 | gnvs->scd0 = (uintptr_t)gpio_dwx_address(cfg->sdcard_cd_gpio); |
Shaunak Saha | 60b4618 | 2016-08-02 17:25:13 -0700 | [diff] [blame] | 190 | } |
| 191 | |
| 192 | /* Save wake source information for calculating ACPI _SWS values */ |
| 193 | int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) |
| 194 | { |
| 195 | struct chipset_power_state *ps; |
| 196 | static uint32_t gpe0_sts[GPE0_REG_MAX]; |
| 197 | uint32_t pm1_en; |
| 198 | int i; |
| 199 | |
| 200 | ps = cbmem_find(CBMEM_ID_POWER_STATE); |
| 201 | if (ps == NULL) |
| 202 | return -1; |
| 203 | |
| 204 | /* |
| 205 | * PM1_EN to check the basic wake events which can happen through |
| 206 | * powerbtn or any other wake source like lidopen, key board press etc. |
| 207 | * WAK_STS bit is set when the system is in one of the sleep states |
| 208 | * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting |
| 209 | * this bit, the PMC will transition the system to the ON state and |
| 210 | * can only be set by hardware and can only be cleared by writing a one |
| 211 | * to this bit position. |
| 212 | */ |
| 213 | pm1_en = ps->pm1_en | WAK_STS | RTC_EN | PWRBTN_EN; |
| 214 | *pm1 = ps->pm1_sts & pm1_en; |
| 215 | |
| 216 | /* Mask off GPE0 status bits that are not enabled */ |
| 217 | *gpe0 = &gpe0_sts[0]; |
| 218 | for (i = 0; i < GPE0_REG_MAX; i++) |
| 219 | gpe0_sts[i] = ps->gpe0_sts[i] & ps->gpe0_en[i]; |
| 220 | |
| 221 | return GPE0_REG_MAX; |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 222 | } |
| 223 | |
| 224 | void southbridge_inject_dsdt(device_t device) |
| 225 | { |
| 226 | struct global_nvs_t *gnvs; |
| 227 | |
| 228 | gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 229 | |
| 230 | if (gnvs) { |
| 231 | acpi_create_gnvs(gnvs); |
| 232 | acpi_save_gnvs((uintptr_t)gnvs); |
Aaron Durbin | 1ee6f0b | 2016-06-10 15:50:34 -0500 | [diff] [blame] | 233 | /* And tell SMI about it */ |
| 234 | smm_setup_structures(gnvs, NULL, NULL); |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 235 | |
| 236 | /* Add it to DSDT. */ |
| 237 | acpigen_write_scope("\\"); |
| 238 | acpigen_write_name_dword("NVSA", (uintptr_t)gnvs); |
| 239 | acpigen_pop_len(); |
| 240 | } |
| 241 | } |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 242 | static acpi_cstate_t cstate_map[] = { |
| 243 | { |
| 244 | /* C1 */ |
| 245 | .ctype = 1, /* ACPI C1 */ |
| 246 | .latency = 1, |
| 247 | .power = 1000, |
| 248 | .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_FIXED, 0, 0, 0), |
| 249 | }, |
| 250 | { |
| 251 | .ctype = 2, /* ACPI C2 */ |
| 252 | .latency = 50, |
| 253 | .power = 10, |
| 254 | .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0, 0x415), |
| 255 | }, |
| 256 | { |
| 257 | .ctype = 3, /* ACPI C3 */ |
| 258 | .latency = 150, |
| 259 | .power = 10, |
| 260 | .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0, 0x419), |
| 261 | } |
| 262 | }; |
| 263 | |
| 264 | acpi_cstate_t *soc_get_cstate_map(int *entries) |
| 265 | { |
| 266 | *entries = ARRAY_SIZE(cstate_map); |
| 267 | return cstate_map; |
| 268 | } |
| 269 | |
| 270 | uint16_t soc_get_acpi_base_address(void) |
| 271 | { |
| 272 | return ACPI_PMIO_BASE; |
| 273 | } |
Furquan Shaikh | 00a9e38 | 2016-10-20 22:45:26 -0700 | [diff] [blame] | 274 | |
| 275 | static void acpigen_soc_get_dw0_in_local5(uintptr_t addr) |
| 276 | { |
| 277 | /* |
| 278 | * Store (\_SB.GPC0 (addr), Local5) |
| 279 | * \_SB.GPC0 is used to read cfg0 value from dw0. It is defined in |
| 280 | * gpiolib.asl. |
| 281 | */ |
| 282 | acpigen_write_store(); |
| 283 | acpigen_emit_namestring("\\_SB.GPC0"); |
| 284 | acpigen_write_integer(addr); |
| 285 | acpigen_emit_byte(LOCAL5_OP); |
| 286 | } |
| 287 | |
| 288 | static int acpigen_soc_get_gpio_val(unsigned int gpio_num, uint32_t mask) |
| 289 | { |
| 290 | assert (gpio_num < TOTAL_PADS); |
| 291 | uintptr_t addr = (uintptr_t)gpio_dwx_address(gpio_num); |
| 292 | |
| 293 | acpigen_soc_get_dw0_in_local5(addr); |
| 294 | |
| 295 | /* If (And (Local5, mask)) */ |
| 296 | acpigen_write_if_and(LOCAL5_OP, mask); |
| 297 | |
| 298 | /* Store (One, Local0) */ |
| 299 | acpigen_write_store_ops(ONE_OP, LOCAL0_OP); |
| 300 | |
| 301 | acpigen_pop_len(); /* If */ |
| 302 | |
| 303 | /* Else */ |
| 304 | acpigen_write_else(); |
| 305 | |
| 306 | /* Store (Zero, Local0) */ |
| 307 | acpigen_write_store_ops(ZERO_OP, LOCAL0_OP); |
| 308 | |
| 309 | acpigen_pop_len(); /* Else */ |
| 310 | |
| 311 | return 0; |
| 312 | } |
| 313 | |
| 314 | static int acpigen_soc_set_gpio_val(unsigned int gpio_num, uint32_t val) |
| 315 | { |
| 316 | assert (gpio_num < TOTAL_PADS); |
| 317 | uintptr_t addr = (uintptr_t)gpio_dwx_address(gpio_num); |
| 318 | |
| 319 | acpigen_soc_get_dw0_in_local5(addr); |
| 320 | |
| 321 | if (val) { |
| 322 | /* Or (Local5, PAD_CFG0_TX_STATE, Local5) */ |
| 323 | acpigen_write_or(LOCAL5_OP, PAD_CFG0_TX_STATE, LOCAL5_OP); |
| 324 | } else { |
| 325 | /* Not (PAD_CFG0_TX_STATE, Local6) */ |
| 326 | acpigen_write_not(PAD_CFG0_TX_STATE, LOCAL6_OP); |
| 327 | |
| 328 | /* And (Local5, Local6, Local5) */ |
| 329 | acpigen_write_and(LOCAL5_OP, LOCAL6_OP, LOCAL5_OP); |
| 330 | } |
| 331 | |
| 332 | /* |
| 333 | * \_SB.SPC0 (addr, Local5) |
| 334 | * \_SB.SPC0 is used to write cfg0 value in dw0. It is defined in |
| 335 | * gpiolib.asl. |
| 336 | */ |
| 337 | acpigen_emit_namestring("\\_SB.SPC0"); |
| 338 | acpigen_write_integer(addr); |
| 339 | acpigen_emit_byte(LOCAL5_OP); |
| 340 | |
| 341 | return 0; |
| 342 | } |
| 343 | |
| 344 | int acpigen_soc_read_rx_gpio(unsigned int gpio_num) |
| 345 | { |
| 346 | return acpigen_soc_get_gpio_val(gpio_num, PAD_CFG0_RX_STATE); |
| 347 | } |
| 348 | |
| 349 | int acpigen_soc_get_tx_gpio(unsigned int gpio_num) |
| 350 | { |
| 351 | return acpigen_soc_get_gpio_val(gpio_num, PAD_CFG0_TX_STATE); |
| 352 | } |
| 353 | |
| 354 | int acpigen_soc_set_tx_gpio(unsigned int gpio_num) |
| 355 | { |
| 356 | return acpigen_soc_set_gpio_val(gpio_num, 1); |
| 357 | } |
| 358 | |
| 359 | int acpigen_soc_clear_tx_gpio(unsigned int gpio_num) |
| 360 | { |
| 361 | return acpigen_soc_set_gpio_val(gpio_num, 0); |
| 362 | } |