Aaron Durbin | 595688a | 2016-03-31 11:38:13 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2016 Intel Corp. |
| 5 | * Copyright 2016 Google Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
Martin Roth | ebabfad | 2016-04-10 11:09:16 -0600 | [diff] [blame] | 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Aaron Durbin | 595688a | 2016-03-31 11:38:13 -0500 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #include <arch/cpu.h> |
Furquan Shaikh | 0b6ff78 | 2016-04-21 08:10:02 -0700 | [diff] [blame] | 19 | #include <assert.h> |
Barnali Sarkar | 66fe0c4 | 2017-05-23 18:17:14 +0530 | [diff] [blame^] | 20 | #include <cpu/x86/msr.h> |
| 21 | #include <intelblocks/msr.h> |
Aaron Durbin | 595688a | 2016-03-31 11:38:13 -0500 | [diff] [blame] | 22 | #include <program_loading.h> |
Aaron Durbin | 595688a | 2016-03-31 11:38:13 -0500 | [diff] [blame] | 23 | |
| 24 | /* |
| 25 | * This file supports the necessary hoops one needs to jump through since |
| 26 | * early FSP component and early stages are running from cache-as-ram. |
| 27 | */ |
| 28 | |
| 29 | static void flush_l1d_to_l2(void) |
| 30 | { |
| 31 | msr_t msr = rdmsr(MSR_POWER_MISC); |
Andrey Petrov | 89e39b5 | 2016-11-30 17:58:38 -0800 | [diff] [blame] | 32 | msr.lo |= FLUSH_DL1_L2; |
Aaron Durbin | 595688a | 2016-03-31 11:38:13 -0500 | [diff] [blame] | 33 | wrmsr(MSR_POWER_MISC, msr); |
| 34 | } |
| 35 | |
Furquan Shaikh | 0b6ff78 | 2016-04-21 08:10:02 -0700 | [diff] [blame] | 36 | static inline int is_car_addr(uintptr_t addr) |
| 37 | { |
| 38 | return ((addr >= CONFIG_DCACHE_RAM_BASE) && |
| 39 | (addr < (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE))); |
| 40 | } |
| 41 | |
Aaron Durbin | faa74b0 | 2016-03-31 14:00:47 -0500 | [diff] [blame] | 42 | void platform_segment_loaded(uintptr_t start, size_t size, int flags) |
Aaron Durbin | 595688a | 2016-03-31 11:38:13 -0500 | [diff] [blame] | 43 | { |
Furquan Shaikh | 0b6ff78 | 2016-04-21 08:10:02 -0700 | [diff] [blame] | 44 | /* Bail out if this is not the final segment. */ |
| 45 | if (!(flags & SEG_FINAL)) |
| 46 | return; |
Aaron Durbin | faa74b0 | 2016-03-31 14:00:47 -0500 | [diff] [blame] | 47 | |
Furquan Shaikh | 0b6ff78 | 2016-04-21 08:10:02 -0700 | [diff] [blame] | 48 | char start_car_check = is_car_addr(start); |
| 49 | char end_car_check = is_car_addr(start + size - 1); |
| 50 | |
| 51 | /* Bail out if loaded program segment does not lie in CAR region. */ |
| 52 | if (!start_car_check && !end_car_check) |
| 53 | return; |
| 54 | |
| 55 | /* Loaded program segment should lie entirely within CAR region. */ |
Lee Leahy | d8fb362 | 2017-03-09 10:10:25 -0800 | [diff] [blame] | 56 | assert(start_car_check && end_car_check); |
Furquan Shaikh | 0b6ff78 | 2016-04-21 08:10:02 -0700 | [diff] [blame] | 57 | |
| 58 | flush_l1d_to_l2(); |
Aaron Durbin | 595688a | 2016-03-31 11:38:13 -0500 | [diff] [blame] | 59 | } |