Aaron Durbin | 595688a | 2016-03-31 11:38:13 -0500 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2016 Intel Corp. |
| 5 | * Copyright 2016 Google Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | */ |
| 12 | |
| 13 | #include <arch/cpu.h> |
| 14 | #include <program_loading.h> |
| 15 | #include <soc/cpu.h> |
| 16 | |
| 17 | /* |
| 18 | * This file supports the necessary hoops one needs to jump through since |
| 19 | * early FSP component and early stages are running from cache-as-ram. |
| 20 | */ |
| 21 | |
| 22 | static void flush_l1d_to_l2(void) |
| 23 | { |
| 24 | msr_t msr = rdmsr(MSR_POWER_MISC); |
| 25 | msr.lo |= (1 << 8); |
| 26 | wrmsr(MSR_POWER_MISC, msr); |
| 27 | } |
| 28 | |
| 29 | void platform_prog_run(struct prog *prog) |
| 30 | { |
| 31 | /* Flush L1D cache to L2 */ |
| 32 | flush_l1d_to_l2(); |
| 33 | } |