Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2011 The Chromium OS Authors. |
| 3 | * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. |
Werner Zeh | bd366ab | 2016-09-05 07:40:29 +0200 | [diff] [blame] | 4 | * Copyright (C) 2016 Siemens AG |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; either version 2 of |
| 9 | * the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but without any warranty; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | /* This file is derived from the flashrom project. */ |
| 18 | #include <stdint.h> |
| 19 | #include <stdlib.h> |
| 20 | #include <string.h> |
| 21 | #include <delay.h> |
| 22 | #include <arch/io.h> |
| 23 | #include <console/console.h> |
| 24 | #include <device/pci_ids.h> |
Furquan Shaikh | 52896c6 | 2016-11-22 11:43:58 -0800 | [diff] [blame] | 25 | #include <spi_flash.h> |
Furquan Shaikh | c28984d | 2016-11-20 21:04:00 -0800 | [diff] [blame] | 26 | #include <spi-generic.h> |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 27 | |
Ben Gardner | fa6014a | 2015-12-08 21:20:25 -0600 | [diff] [blame] | 28 | #include <soc/lpc.h> |
| 29 | #include <soc/pci_devs.h> |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 30 | |
| 31 | #ifdef __SMM__ |
| 32 | #define pci_read_config_byte(dev, reg, targ)\ |
| 33 | *(targ) = pci_read_config8(dev, reg) |
| 34 | #define pci_read_config_word(dev, reg, targ)\ |
| 35 | *(targ) = pci_read_config16(dev, reg) |
| 36 | #define pci_read_config_dword(dev, reg, targ)\ |
| 37 | *(targ) = pci_read_config32(dev, reg) |
| 38 | #define pci_write_config_byte(dev, reg, val)\ |
| 39 | pci_write_config8(dev, reg, val) |
| 40 | #define pci_write_config_word(dev, reg, val)\ |
| 41 | pci_write_config16(dev, reg, val) |
| 42 | #define pci_write_config_dword(dev, reg, val)\ |
| 43 | pci_write_config32(dev, reg, val) |
| 44 | #else /* !__SMM__ */ |
| 45 | #include <device/device.h> |
| 46 | #include <device/pci.h> |
| 47 | #define pci_read_config_byte(dev, reg, targ)\ |
| 48 | *(targ) = pci_read_config8(dev, reg) |
| 49 | #define pci_read_config_word(dev, reg, targ)\ |
| 50 | *(targ) = pci_read_config16(dev, reg) |
| 51 | #define pci_read_config_dword(dev, reg, targ)\ |
| 52 | *(targ) = pci_read_config32(dev, reg) |
| 53 | #define pci_write_config_byte(dev, reg, val)\ |
| 54 | pci_write_config8(dev, reg, val) |
| 55 | #define pci_write_config_word(dev, reg, val)\ |
| 56 | pci_write_config16(dev, reg, val) |
| 57 | #define pci_write_config_dword(dev, reg, val)\ |
| 58 | pci_write_config32(dev, reg, val) |
| 59 | #endif /* !__SMM__ */ |
| 60 | |
| 61 | typedef struct spi_slave ich_spi_slave; |
| 62 | |
| 63 | static int ichspi_lock = 0; |
| 64 | |
| 65 | typedef struct ich9_spi_regs { |
| 66 | uint32_t bfpr; |
| 67 | uint16_t hsfs; |
| 68 | uint16_t hsfc; |
| 69 | uint32_t faddr; |
| 70 | uint32_t _reserved0; |
| 71 | uint32_t fdata[16]; |
| 72 | uint32_t frap; |
| 73 | uint32_t freg[5]; |
| 74 | uint32_t _reserved1[3]; |
| 75 | uint32_t pr[5]; |
| 76 | uint32_t _reserved2[2]; |
| 77 | uint8_t ssfs; |
| 78 | uint8_t ssfc[3]; |
| 79 | uint16_t preop; |
| 80 | uint16_t optype; |
| 81 | uint8_t opmenu[8]; |
Ben Gardner | fad2313 | 2015-12-07 11:33:45 -0600 | [diff] [blame] | 82 | uint8_t _reserved3[16]; |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 83 | uint32_t fdoc; |
| 84 | uint32_t fdod; |
| 85 | uint8_t _reserved4[8]; |
| 86 | uint32_t afc; |
| 87 | uint32_t lvscc; |
| 88 | uint32_t uvscc; |
| 89 | uint8_t _reserved5[4]; |
| 90 | uint32_t fpb; |
| 91 | uint8_t _reserved6[28]; |
| 92 | uint32_t srdl; |
| 93 | uint32_t srdc; |
| 94 | uint32_t srd; |
| 95 | } __attribute__((packed)) ich9_spi_regs; |
| 96 | |
| 97 | typedef struct ich_spi_controller { |
| 98 | int locked; |
| 99 | |
| 100 | uint8_t *opmenu; |
| 101 | int menubytes; |
| 102 | uint16_t *preop; |
| 103 | uint16_t *optype; |
| 104 | uint32_t *addr; |
| 105 | uint8_t *data; |
| 106 | unsigned databytes; |
| 107 | uint8_t *status; |
| 108 | uint16_t *control; |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 109 | } ich_spi_controller; |
| 110 | |
| 111 | static ich_spi_controller cntlr; |
| 112 | |
| 113 | enum { |
| 114 | SPIS_SCIP = 0x0001, |
| 115 | SPIS_GRANT = 0x0002, |
| 116 | SPIS_CDS = 0x0004, |
| 117 | SPIS_FCERR = 0x0008, |
| 118 | SSFS_AEL = 0x0010, |
| 119 | SPIS_LOCK = 0x8000, |
| 120 | SPIS_RESERVED_MASK = 0x7ff0, |
| 121 | SSFS_RESERVED_MASK = 0x7fe2 |
| 122 | }; |
| 123 | |
| 124 | enum { |
| 125 | SPIC_SCGO = 0x000002, |
| 126 | SPIC_ACS = 0x000004, |
| 127 | SPIC_SPOP = 0x000008, |
| 128 | SPIC_DBC = 0x003f00, |
| 129 | SPIC_DS = 0x004000, |
| 130 | SPIC_SME = 0x008000, |
| 131 | SSFC_SCF_MASK = 0x070000, |
| 132 | SSFC_RESERVED = 0xf80000 |
| 133 | }; |
| 134 | |
| 135 | enum { |
| 136 | HSFS_FDONE = 0x0001, |
| 137 | HSFS_FCERR = 0x0002, |
| 138 | HSFS_AEL = 0x0004, |
| 139 | HSFS_BERASE_MASK = 0x0018, |
| 140 | HSFS_BERASE_SHIFT = 3, |
| 141 | HSFS_SCIP = 0x0020, |
| 142 | HSFS_FDOPSS = 0x2000, |
| 143 | HSFS_FDV = 0x4000, |
| 144 | HSFS_FLOCKDN = 0x8000 |
| 145 | }; |
| 146 | |
| 147 | enum { |
| 148 | HSFC_FGO = 0x0001, |
| 149 | HSFC_FCYCLE_MASK = 0x0006, |
| 150 | HSFC_FCYCLE_SHIFT = 1, |
| 151 | HSFC_FDBC_MASK = 0x3f00, |
| 152 | HSFC_FDBC_SHIFT = 8, |
| 153 | HSFC_FSMIE = 0x8000 |
| 154 | }; |
| 155 | |
| 156 | enum { |
| 157 | SPI_OPCODE_TYPE_READ_NO_ADDRESS = 0, |
| 158 | SPI_OPCODE_TYPE_WRITE_NO_ADDRESS = 1, |
| 159 | SPI_OPCODE_TYPE_READ_WITH_ADDRESS = 2, |
| 160 | SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 |
| 161 | }; |
| 162 | |
Werner Zeh | bd366ab | 2016-09-05 07:40:29 +0200 | [diff] [blame] | 163 | #define SPI_OFFSET_MASK 0x3ff |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 164 | |
Werner Zeh | bd366ab | 2016-09-05 07:40:29 +0200 | [diff] [blame] | 165 | static uint8_t readb_(const void *addr) |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 166 | { |
Werner Zeh | bd366ab | 2016-09-05 07:40:29 +0200 | [diff] [blame] | 167 | uint8_t v = read8(addr); |
| 168 | if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { |
| 169 | printk(BIOS_DEBUG, "SPI: read %2.2x from %4.4x\n", |
| 170 | v, (((uint32_t) addr) & SPI_OFFSET_MASK)); |
| 171 | } |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 172 | return v; |
| 173 | } |
| 174 | |
Werner Zeh | bd366ab | 2016-09-05 07:40:29 +0200 | [diff] [blame] | 175 | static uint16_t readw_(const void *addr) |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 176 | { |
Werner Zeh | bd366ab | 2016-09-05 07:40:29 +0200 | [diff] [blame] | 177 | uint16_t v = read16(addr); |
| 178 | if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { |
| 179 | printk(BIOS_DEBUG, "SPI: read %4.4x from %4.4x\n", |
| 180 | v, (((uint32_t) addr) & SPI_OFFSET_MASK)); |
| 181 | } |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 182 | return v; |
| 183 | } |
| 184 | |
Werner Zeh | bd366ab | 2016-09-05 07:40:29 +0200 | [diff] [blame] | 185 | static uint32_t readl_(const void *addr) |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 186 | { |
Werner Zeh | bd366ab | 2016-09-05 07:40:29 +0200 | [diff] [blame] | 187 | uint32_t v = read32(addr); |
| 188 | if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { |
| 189 | printk(BIOS_DEBUG, "SPI: read %8.8x from %4.4x\n", |
| 190 | v, (((uint32_t) addr) & SPI_OFFSET_MASK)); |
| 191 | } |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 192 | return v; |
| 193 | } |
| 194 | |
Werner Zeh | bd366ab | 2016-09-05 07:40:29 +0200 | [diff] [blame] | 195 | static void writeb_(uint8_t b, void *addr) |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 196 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 197 | write8(addr, b); |
Werner Zeh | bd366ab | 2016-09-05 07:40:29 +0200 | [diff] [blame] | 198 | if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { |
| 199 | printk(BIOS_DEBUG, "SPI: wrote %2.2x to %4.4x\n", |
| 200 | b, (((uint32_t) addr) & SPI_OFFSET_MASK)); |
| 201 | } |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 202 | } |
| 203 | |
Werner Zeh | bd366ab | 2016-09-05 07:40:29 +0200 | [diff] [blame] | 204 | static void writew_(uint16_t b, void *addr) |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 205 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 206 | write16(addr, b); |
Werner Zeh | bd366ab | 2016-09-05 07:40:29 +0200 | [diff] [blame] | 207 | if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { |
| 208 | printk(BIOS_DEBUG, "SPI: wrote %4.4x to %4.4x\n", |
| 209 | b, (((uint32_t) addr) & SPI_OFFSET_MASK)); |
| 210 | } |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 211 | } |
| 212 | |
Werner Zeh | bd366ab | 2016-09-05 07:40:29 +0200 | [diff] [blame] | 213 | static void writel_(uint32_t b, void *addr) |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 214 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 215 | write32(addr, b); |
Werner Zeh | bd366ab | 2016-09-05 07:40:29 +0200 | [diff] [blame] | 216 | if (IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)) { |
| 217 | printk(BIOS_DEBUG, "SPI: wrote %8.8x to %4.4x\n", |
| 218 | b, (((uint32_t) addr) & SPI_OFFSET_MASK)); |
| 219 | } |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 220 | } |
| 221 | |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 222 | static void write_reg(const void *value, void *dest, uint32_t size) |
| 223 | { |
| 224 | const uint8_t *bvalue = value; |
| 225 | uint8_t *bdest = dest; |
| 226 | |
| 227 | while (size >= 4) { |
| 228 | writel_(*(const uint32_t *)bvalue, bdest); |
| 229 | bdest += 4; bvalue += 4; size -= 4; |
| 230 | } |
| 231 | while (size) { |
| 232 | writeb_(*bvalue, bdest); |
| 233 | bdest++; bvalue++; size--; |
| 234 | } |
| 235 | } |
| 236 | |
| 237 | static void read_reg(const void *src, void *value, uint32_t size) |
| 238 | { |
| 239 | const uint8_t *bsrc = src; |
| 240 | uint8_t *bvalue = value; |
| 241 | |
| 242 | while (size >= 4) { |
| 243 | *(uint32_t *)bvalue = readl_(bsrc); |
| 244 | bsrc += 4; bvalue += 4; size -= 4; |
| 245 | } |
| 246 | while (size) { |
| 247 | *bvalue = readb_(bsrc); |
| 248 | bsrc++; bvalue++; size--; |
| 249 | } |
| 250 | } |
| 251 | |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 252 | static ich9_spi_regs *spi_regs(void) |
| 253 | { |
| 254 | device_t dev; |
| 255 | uint32_t sbase; |
| 256 | |
| 257 | #ifdef __SMM__ |
| 258 | dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); |
| 259 | #else |
| 260 | dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); |
| 261 | #endif |
| 262 | pci_read_config_dword(dev, SBASE, &sbase); |
| 263 | sbase &= ~0x1ff; |
| 264 | |
| 265 | return (void *)sbase; |
| 266 | } |
| 267 | |
| 268 | void spi_init(void) |
| 269 | { |
| 270 | ich9_spi_regs *ich9_spi = spi_regs(); |
| 271 | |
| 272 | ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN; |
| 273 | cntlr.opmenu = ich9_spi->opmenu; |
| 274 | cntlr.menubytes = sizeof(ich9_spi->opmenu); |
| 275 | cntlr.optype = &ich9_spi->optype; |
| 276 | cntlr.addr = &ich9_spi->faddr; |
| 277 | cntlr.data = (uint8_t *)ich9_spi->fdata; |
| 278 | cntlr.databytes = sizeof(ich9_spi->fdata); |
| 279 | cntlr.status = &ich9_spi->ssfs; |
| 280 | cntlr.control = (uint16_t *)ich9_spi->ssfc; |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 281 | cntlr.preop = &ich9_spi->preop; |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 282 | } |
| 283 | |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 284 | typedef struct spi_transaction { |
| 285 | const uint8_t *out; |
| 286 | uint32_t bytesout; |
| 287 | uint8_t *in; |
| 288 | uint32_t bytesin; |
| 289 | uint8_t type; |
| 290 | uint8_t opcode; |
| 291 | uint32_t offset; |
| 292 | } spi_transaction; |
| 293 | |
| 294 | static inline void spi_use_out(spi_transaction *trans, unsigned bytes) |
| 295 | { |
| 296 | trans->out += bytes; |
| 297 | trans->bytesout -= bytes; |
| 298 | } |
| 299 | |
| 300 | static inline void spi_use_in(spi_transaction *trans, unsigned bytes) |
| 301 | { |
| 302 | trans->in += bytes; |
| 303 | trans->bytesin -= bytes; |
| 304 | } |
| 305 | |
| 306 | static void spi_setup_type(spi_transaction *trans) |
| 307 | { |
| 308 | trans->type = 0xFF; |
| 309 | |
| 310 | /* Try to guess spi type from read/write sizes. */ |
| 311 | if (trans->bytesin == 0) { |
| 312 | if (trans->bytesout > 4) |
| 313 | /* |
| 314 | * If bytesin = 0 and bytesout > 4, we presume this is |
| 315 | * a write data operation, which is accompanied by an |
| 316 | * address. |
| 317 | */ |
| 318 | trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS; |
| 319 | else |
| 320 | trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS; |
| 321 | return; |
| 322 | } |
| 323 | |
| 324 | if (trans->bytesout == 1) { /* and bytesin is > 0 */ |
| 325 | trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS; |
| 326 | return; |
| 327 | } |
| 328 | |
| 329 | if (trans->bytesout == 4) { /* and bytesin is > 0 */ |
| 330 | trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; |
| 331 | } |
| 332 | |
| 333 | /* Fast read command is called with 5 bytes instead of 4 */ |
| 334 | if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) { |
| 335 | trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS; |
| 336 | --trans->bytesout; |
| 337 | } |
| 338 | } |
| 339 | |
| 340 | static int spi_setup_opcode(spi_transaction *trans) |
| 341 | { |
| 342 | uint16_t optypes; |
| 343 | uint8_t opmenu[cntlr.menubytes]; |
| 344 | |
| 345 | trans->opcode = trans->out[0]; |
| 346 | spi_use_out(trans, 1); |
| 347 | if (!ichspi_lock) { |
| 348 | /* The lock is off, so just use index 0. */ |
| 349 | writeb_(trans->opcode, cntlr.opmenu); |
| 350 | optypes = readw_(cntlr.optype); |
| 351 | optypes = (optypes & 0xfffc) | (trans->type & 0x3); |
| 352 | writew_(optypes, cntlr.optype); |
| 353 | return 0; |
| 354 | } else { |
| 355 | /* The lock is on. See if what we need is on the menu. */ |
| 356 | uint8_t optype; |
| 357 | uint16_t opcode_index; |
| 358 | |
| 359 | /* Write Enable is handled as atomic prefix */ |
| 360 | if (trans->opcode == SPI_OPCODE_WREN) |
| 361 | return 0; |
| 362 | |
| 363 | read_reg(cntlr.opmenu, opmenu, sizeof(opmenu)); |
| 364 | for (opcode_index = 0; opcode_index < cntlr.menubytes; |
| 365 | opcode_index++) { |
| 366 | if (opmenu[opcode_index] == trans->opcode) |
| 367 | break; |
| 368 | } |
| 369 | |
| 370 | if (opcode_index == cntlr.menubytes) { |
| 371 | printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n", |
| 372 | trans->opcode); |
| 373 | return -1; |
| 374 | } |
| 375 | |
| 376 | optypes = readw_(cntlr.optype); |
| 377 | optype = (optypes >> (opcode_index * 2)) & 0x3; |
| 378 | if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS && |
| 379 | optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS && |
| 380 | trans->bytesout >= 3) { |
| 381 | /* We guessed wrong earlier. Fix it up. */ |
| 382 | trans->type = optype; |
| 383 | } |
| 384 | if (optype != trans->type) { |
| 385 | printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n", |
| 386 | optype); |
| 387 | return -1; |
| 388 | } |
| 389 | return opcode_index; |
| 390 | } |
| 391 | } |
| 392 | |
| 393 | static int spi_setup_offset(spi_transaction *trans) |
| 394 | { |
| 395 | /* Separate the SPI address and data. */ |
| 396 | switch (trans->type) { |
| 397 | case SPI_OPCODE_TYPE_READ_NO_ADDRESS: |
| 398 | case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS: |
| 399 | return 0; |
| 400 | case SPI_OPCODE_TYPE_READ_WITH_ADDRESS: |
| 401 | case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS: |
| 402 | trans->offset = ((uint32_t)trans->out[0] << 16) | |
| 403 | ((uint32_t)trans->out[1] << 8) | |
| 404 | ((uint32_t)trans->out[2] << 0); |
| 405 | spi_use_out(trans, 3); |
| 406 | return 1; |
| 407 | default: |
| 408 | printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n", trans->type); |
| 409 | return -1; |
| 410 | } |
| 411 | } |
| 412 | |
| 413 | /* |
| 414 | * Wait for up to 60ms til status register bit(s) turn 1 (in case wait_til_set |
| 415 | * below is True) or 0. In case the wait was for the bit(s) to set - write |
| 416 | * those bits back, which would cause resetting them. |
| 417 | * |
| 418 | * Return the last read status value on success or -1 on failure. |
| 419 | */ |
Werner Zeh | bd366ab | 2016-09-05 07:40:29 +0200 | [diff] [blame] | 420 | static int ich_status_poll(uint16_t bitmask, int wait_til_set) |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 421 | { |
| 422 | int timeout = 40000; /* This will result in 400 ms */ |
Werner Zeh | bd366ab | 2016-09-05 07:40:29 +0200 | [diff] [blame] | 423 | uint16_t status = 0; |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 424 | |
| 425 | while (timeout--) { |
| 426 | status = readw_(cntlr.status); |
| 427 | if (wait_til_set ^ ((status & bitmask) == 0)) { |
| 428 | if (wait_til_set) |
| 429 | writew_((status & bitmask), cntlr.status); |
| 430 | return status; |
| 431 | } |
| 432 | udelay(10); |
| 433 | } |
| 434 | |
| 435 | printk(BIOS_DEBUG, "ICH SPI: SCIP timeout, read %x, expected %x\n", |
| 436 | status, bitmask); |
| 437 | return -1; |
| 438 | } |
| 439 | |
Kyösti Mälkki | 1110495 | 2014-06-29 16:17:33 +0300 | [diff] [blame] | 440 | unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) |
| 441 | { |
| 442 | return min(cntlr.databytes, buf_len); |
| 443 | } |
| 444 | |
Furquan Shaikh | 94f8699 | 2016-12-01 07:12:32 -0800 | [diff] [blame] | 445 | static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, |
| 446 | size_t bytesout, void *din, size_t bytesin) |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 447 | { |
| 448 | uint16_t control; |
| 449 | int16_t opcode_index; |
| 450 | int with_address; |
| 451 | int status; |
| 452 | |
| 453 | spi_transaction trans = { |
Gabe Black | 93d9f92 | 2014-03-27 21:52:43 -0700 | [diff] [blame] | 454 | dout, bytesout, |
| 455 | din, bytesin, |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 456 | 0xff, 0xff, 0 |
| 457 | }; |
| 458 | |
| 459 | /* There has to always at least be an opcode. */ |
Gabe Black | 93d9f92 | 2014-03-27 21:52:43 -0700 | [diff] [blame] | 460 | if (!bytesout || !dout) { |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 461 | printk(BIOS_DEBUG, "ICH SPI: No opcode for transfer\n"); |
| 462 | return -1; |
| 463 | } |
| 464 | /* Make sure if we read something we have a place to put it. */ |
Gabe Black | 93d9f92 | 2014-03-27 21:52:43 -0700 | [diff] [blame] | 465 | if (bytesin != 0 && !din) { |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 466 | printk(BIOS_DEBUG, "ICH SPI: Read but no target buffer\n"); |
| 467 | return -1; |
| 468 | } |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 469 | |
| 470 | if (ich_status_poll(SPIS_SCIP, 0) == -1) |
| 471 | return -1; |
| 472 | |
| 473 | writew_(SPIS_CDS | SPIS_FCERR, cntlr.status); |
| 474 | |
| 475 | spi_setup_type(&trans); |
| 476 | if ((opcode_index = spi_setup_opcode(&trans)) < 0) |
| 477 | return -1; |
| 478 | if ((with_address = spi_setup_offset(&trans)) < 0) |
| 479 | return -1; |
| 480 | |
| 481 | if (!ichspi_lock && trans.opcode == SPI_OPCODE_WREN) { |
| 482 | /* |
| 483 | * Treat Write Enable as Atomic Pre-Op if possible |
| 484 | * in order to prevent the Management Engine from |
| 485 | * issuing a transaction between WREN and DATA. |
| 486 | */ |
| 487 | writew_(trans.opcode, cntlr.preop); |
| 488 | return 0; |
| 489 | } |
| 490 | |
| 491 | /* Preset control fields */ |
| 492 | control = SPIC_SCGO | ((opcode_index & 0x07) << 4); |
| 493 | |
| 494 | /* Issue atomic preop cycle if needed */ |
| 495 | if (readw_(cntlr.preop)) |
| 496 | control |= SPIC_ACS; |
| 497 | |
| 498 | if (!trans.bytesout && !trans.bytesin) { |
| 499 | /* SPI addresses are 24 bit only */ |
| 500 | if (with_address) |
| 501 | writel_(trans.offset & 0x00FFFFFF, cntlr.addr); |
| 502 | |
| 503 | /* |
| 504 | * This is a 'no data' command (like Write Enable), its |
Martin Roth | 7c96629 | 2014-12-07 14:59:46 -0700 | [diff] [blame] | 505 | * bytesout size was 1, decremented to zero while executing |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 506 | * spi_setup_opcode() above. Tell the chip to send the |
| 507 | * command. |
| 508 | */ |
| 509 | writew_(control, cntlr.control); |
| 510 | |
| 511 | /* wait for the result */ |
| 512 | status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); |
| 513 | if (status == -1) |
| 514 | return -1; |
| 515 | |
| 516 | if (status & SPIS_FCERR) { |
| 517 | printk(BIOS_DEBUG, "ICH SPI: Command transaction error\n"); |
| 518 | return -1; |
| 519 | } |
| 520 | |
| 521 | goto spi_xfer_exit; |
| 522 | } |
| 523 | |
| 524 | /* |
| 525 | * Check if this is a write command attempting to transfer more bytes |
| 526 | * than the controller can handle. Iterations for writes are not |
| 527 | * supported here because each SPI write command needs to be preceded |
| 528 | * and followed by other SPI commands, and this sequence is controlled |
| 529 | * by the SPI chip driver. |
| 530 | */ |
| 531 | if (trans.bytesout > cntlr.databytes) { |
| 532 | printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use" |
Kyösti Mälkki | 1110495 | 2014-06-29 16:17:33 +0300 | [diff] [blame] | 533 | " spi_crop_chunk()?\n"); |
Martin Roth | 433659a | 2014-05-12 21:55:00 -0600 | [diff] [blame] | 534 | return -1; |
| 535 | } |
| 536 | |
| 537 | /* |
| 538 | * Read or write up to databytes bytes at a time until everything has |
| 539 | * been sent. |
| 540 | */ |
| 541 | while (trans.bytesout || trans.bytesin) { |
| 542 | uint32_t data_length; |
| 543 | |
| 544 | /* SPI addresses are 24 bit only */ |
| 545 | writel_(trans.offset & 0x00FFFFFF, cntlr.addr); |
| 546 | |
| 547 | if (trans.bytesout) |
| 548 | data_length = min(trans.bytesout, cntlr.databytes); |
| 549 | else |
| 550 | data_length = min(trans.bytesin, cntlr.databytes); |
| 551 | |
| 552 | /* Program data into FDATA0 to N */ |
| 553 | if (trans.bytesout) { |
| 554 | write_reg(trans.out, cntlr.data, data_length); |
| 555 | spi_use_out(&trans, data_length); |
| 556 | if (with_address) |
| 557 | trans.offset += data_length; |
| 558 | } |
| 559 | |
| 560 | /* Add proper control fields' values */ |
| 561 | control &= ~((cntlr.databytes - 1) << 8); |
| 562 | control |= SPIC_DS; |
| 563 | control |= (data_length - 1) << 8; |
| 564 | |
| 565 | /* write it */ |
| 566 | writew_(control, cntlr.control); |
| 567 | |
| 568 | /* Wait for Cycle Done Status or Flash Cycle Error. */ |
| 569 | status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1); |
| 570 | if (status == -1) |
| 571 | return -1; |
| 572 | |
| 573 | if (status & SPIS_FCERR) { |
| 574 | printk(BIOS_DEBUG, "ICH SPI: Data transaction error\n"); |
| 575 | return -1; |
| 576 | } |
| 577 | |
| 578 | if (trans.bytesin) { |
| 579 | read_reg(cntlr.data, trans.in, data_length); |
| 580 | spi_use_in(&trans, data_length); |
| 581 | if (with_address) |
| 582 | trans.offset += data_length; |
| 583 | } |
| 584 | } |
| 585 | |
| 586 | spi_xfer_exit: |
| 587 | /* Clear atomic preop now that xfer is done */ |
| 588 | writew_(0, cntlr.preop); |
| 589 | |
| 590 | return 0; |
| 591 | } |
Furquan Shaikh | 94f8699 | 2016-12-01 07:12:32 -0800 | [diff] [blame] | 592 | |
| 593 | static const struct spi_ctrlr spi_ctrlr = { |
| 594 | .xfer = spi_ctrlr_xfer, |
Furquan Shaikh | c2973d1 | 2016-11-29 22:07:42 -0800 | [diff] [blame] | 595 | .xfer_vector = spi_xfer_two_vectors, |
Furquan Shaikh | 94f8699 | 2016-12-01 07:12:32 -0800 | [diff] [blame] | 596 | }; |
| 597 | |
| 598 | int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) |
| 599 | { |
| 600 | slave->bus = bus; |
| 601 | slave->cs = cs; |
| 602 | slave->ctrlr = &spi_ctrlr; |
| 603 | return 0; |
| 604 | } |