Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015 Intel Corp. |
| 5 | * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.) |
| 6 | * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.) |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
Martin Roth | ebabfad | 2016-04-10 11:09:16 -0600 | [diff] [blame] | 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 17 | */ |
| 18 | |
Aaron Durbin | eebe0e0 | 2016-03-18 11:19:38 -0500 | [diff] [blame] | 19 | #include <arch/cpu.h> |
Ravi Sarawadi | 2da008a | 2016-04-27 15:20:14 -0700 | [diff] [blame] | 20 | #include <arch/early_variables.h> |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 21 | #include <arch/io.h> |
| 22 | #include <arch/symbols.h> |
Ravi Sarawadi | 2da008a | 2016-04-27 15:20:14 -0700 | [diff] [blame] | 23 | #include <assert.h> |
Furquan Shaikh | bae6383 | 2016-06-17 15:50:24 -0700 | [diff] [blame] | 24 | #include <bootmode.h> |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 25 | #include <cbfs.h> |
| 26 | #include <cbmem.h> |
| 27 | #include <console/console.h> |
Andrey Petrov | f748f83 | 2016-04-23 13:15:51 -0700 | [diff] [blame] | 28 | #include <cpu/x86/mtrr.h> |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 29 | #include <device/pci_def.h> |
Ravi Sarawadi | 2da008a | 2016-04-27 15:20:14 -0700 | [diff] [blame] | 30 | #include <device/resource.h> |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 31 | #include <fsp/api.h> |
Brandon Breitenstein | 135eae9 | 2016-09-30 13:57:12 -0700 | [diff] [blame] | 32 | #include <fsp/memmap.h> |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 33 | #include <fsp/util.h> |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 34 | #include <soc/cpu.h> |
Furquan Shaikh | d6c5559 | 2016-11-21 12:41:20 -0800 | [diff] [blame] | 35 | #include <soc/flash_ctrlr.h> |
Andrey Petrov | 96e9ff1 | 2016-11-04 16:18:30 -0700 | [diff] [blame] | 36 | #include <soc/intel/common/mrc_cache.h> |
Ravi Sarawadi | 2da008a | 2016-04-27 15:20:14 -0700 | [diff] [blame] | 37 | #include <soc/iomap.h> |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 38 | #include <soc/northbridge.h> |
Ravi Sarawadi | 2da008a | 2016-04-27 15:20:14 -0700 | [diff] [blame] | 39 | #include <soc/pci_devs.h> |
| 40 | #include <soc/pm.h> |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 41 | #include <soc/romstage.h> |
| 42 | #include <soc/uart.h> |
Furquan Shaikh | d6c5559 | 2016-11-21 12:41:20 -0800 | [diff] [blame] | 43 | #include <spi_flash.h> |
Ravi Sarawadi | 2da008a | 2016-04-27 15:20:14 -0700 | [diff] [blame] | 44 | #include <string.h> |
Alexandru Gagniuc | eaa0a17 | 2016-05-16 16:56:28 -0700 | [diff] [blame] | 45 | #include <timestamp.h> |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 46 | #include <timer.h> |
| 47 | #include <delay.h> |
| 48 | #include "chip.h" |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 49 | |
Ravi Sarawadi | 2da008a | 2016-04-27 15:20:14 -0700 | [diff] [blame] | 50 | static struct chipset_power_state power_state CAR_GLOBAL; |
| 51 | |
Andrey Petrov | 96e9ff1 | 2016-11-04 16:18:30 -0700 | [diff] [blame] | 52 | static const uint8_t hob_variable_guid[16] = { |
| 53 | 0x7d, 0x14, 0x34, 0xa0, 0x0c, 0x69, 0x54, 0x41, |
| 54 | 0x8d, 0xe6, 0xc0, 0x44, 0x64, 0x1d, 0xe9, 0x42, |
| 55 | }; |
| 56 | |
| 57 | static uint32_t fsp_version CAR_GLOBAL; |
| 58 | |
Furquan Shaikh | c681409 | 2016-05-04 16:03:36 -0700 | [diff] [blame] | 59 | /* High Performance Event Timer Configuration */ |
| 60 | #define P2SB_HPTC 0x60 |
| 61 | #define P2SB_HPTC_ADDRESS_ENABLE (1 << 7) |
| 62 | /* |
| 63 | * ADDRESS_SELECT ENCODING_RANGE |
| 64 | * 0 0xFED0 0000 - 0xFED0 03FF |
| 65 | * 1 0xFED0 1000 - 0xFED0 13FF |
| 66 | * 2 0xFED0 2000 - 0xFED0 23FF |
| 67 | * 3 0xFED0 3000 - 0xFED0 33FF |
| 68 | */ |
| 69 | #define P2SB_HPTC_ADDRESS_SELECT_0 (0 << 0) |
| 70 | #define P2SB_HPTC_ADDRESS_SELECT_1 (1 << 0) |
| 71 | #define P2SB_HPTC_ADDRESS_SELECT_2 (2 << 0) |
| 72 | #define P2SB_HPTC_ADDRESS_SELECT_3 (3 << 0) |
| 73 | |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 74 | /* |
| 75 | * Enables several BARs and devices which are needed for memory init |
| 76 | * - MCH_BASE_ADDR is needed in order to talk to the memory controller |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 77 | * - HPET is enabled because FSP wants to store a pointer to global data in the |
| 78 | * HPET comparator register |
| 79 | */ |
| 80 | static void soc_early_romstage_init(void) |
| 81 | { |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 82 | /* Set MCH base address and enable bit */ |
| 83 | pci_write_config32(NB_DEV_ROOT, MCHBAR, MCH_BASE_ADDR | 1); |
| 84 | |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 85 | /* Enable decoding for HPET. Needed for FSP global pointer storage */ |
Furquan Shaikh | c681409 | 2016-05-04 16:03:36 -0700 | [diff] [blame] | 86 | pci_write_config8(P2SB_DEV, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 | |
| 87 | P2SB_HPTC_ADDRESS_ENABLE); |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 88 | } |
| 89 | |
| 90 | static void disable_watchdog(void) |
| 91 | { |
| 92 | uint32_t reg; |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 93 | |
| 94 | /* Stop TCO timer */ |
Andrey Petrov | 664d585 | 2016-05-15 22:12:35 -0700 | [diff] [blame] | 95 | reg = inl(ACPI_PMIO_BASE + TCO1_CNT); |
| 96 | reg |= TCO_TMR_HLT; |
| 97 | outl(reg, ACPI_PMIO_BASE + TCO1_CNT); |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 98 | } |
| 99 | |
Ravi Sarawadi | 2da008a | 2016-04-27 15:20:14 -0700 | [diff] [blame] | 100 | static void migrate_power_state(int is_recovery) |
| 101 | { |
| 102 | struct chipset_power_state *ps_cbmem; |
| 103 | struct chipset_power_state *ps_car; |
| 104 | |
| 105 | ps_car = car_get_var_ptr(&power_state); |
| 106 | ps_cbmem = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*ps_cbmem)); |
| 107 | |
| 108 | if (ps_cbmem == NULL) { |
| 109 | printk(BIOS_DEBUG, "Unable to add power state to cbmem!\n"); |
| 110 | return; |
| 111 | } |
| 112 | memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem)); |
| 113 | } |
| 114 | ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state); |
| 115 | |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 116 | /* |
| 117 | * Punit Initialization code. This all isn't documented, but |
| 118 | * this is the recipe. |
| 119 | */ |
| 120 | static bool punit_init(void) |
| 121 | { |
| 122 | uint32_t reg; |
| 123 | uint32_t data; |
| 124 | struct stopwatch sw; |
| 125 | |
| 126 | /* |
| 127 | * Software Core Disable Mask (P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR). |
| 128 | * Enable all cores here. |
| 129 | */ |
| 130 | write32((void *)(MCH_BASE_ADDR + P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR), |
| 131 | 0x0); |
| 132 | |
| 133 | void *bios_rest_cpl = (void *)(MCH_BASE_ADDR + |
| 134 | P_CR_BIOS_RESET_CPL_0_0_0_MCHBAR); |
| 135 | /* P-Unit bring up */ |
| 136 | reg = read32(bios_rest_cpl); |
| 137 | if (reg == 0xffffffff) { |
| 138 | /* P-unit not found */ |
Lee Leahy | a444753 | 2017-03-09 10:45:02 -0800 | [diff] [blame] | 139 | printk(BIOS_DEBUG, "Punit MMIO not available\n"); |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 140 | return false; |
Lee Leahy | a444753 | 2017-03-09 10:45:02 -0800 | [diff] [blame] | 141 | } |
| 142 | /* Set Punit interrupt pin IPIN offset 3D */ |
| 143 | pci_write_config8(PUNIT_DEVFN, PCI_INTERRUPT_PIN, 0x2); |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 144 | |
Lee Leahy | a444753 | 2017-03-09 10:45:02 -0800 | [diff] [blame] | 145 | /* Set PUINT IRQ to 24 and INTPIN LOCK */ |
| 146 | write32((void *)(MCH_BASE_ADDR + PUNIT_THERMAL_DEVICE_IRQ), |
| 147 | PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER | |
| 148 | PUINT_THERMAL_DEVICE_IRQ_LOCK); |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 149 | |
Lee Leahy | a444753 | 2017-03-09 10:45:02 -0800 | [diff] [blame] | 150 | data = read32((void *)(MCH_BASE_ADDR + 0x7818)); |
| 151 | data &= 0xFFFFE01F; |
| 152 | data |= 0x20 | 0x200; |
| 153 | write32((void *)(MCH_BASE_ADDR + 0x7818), data); |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 154 | |
Lee Leahy | a444753 | 2017-03-09 10:45:02 -0800 | [diff] [blame] | 155 | /* Stage0 BIOS Reset Complete (RST_CPL) */ |
| 156 | write32(bios_rest_cpl, 0x1); |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 157 | |
Lee Leahy | a444753 | 2017-03-09 10:45:02 -0800 | [diff] [blame] | 158 | /* |
| 159 | * Poll for bit 8 in same reg (RST_CPL). |
| 160 | * We wait here till 1 ms for the bit to get set. |
| 161 | */ |
| 162 | stopwatch_init_msecs_expire(&sw, 1); |
| 163 | while (!(read32(bios_rest_cpl) & 0x100)) { |
| 164 | if (stopwatch_expired(&sw)) { |
| 165 | printk(BIOS_DEBUG, |
| 166 | "Failed to set RST_CPL bit\n"); |
| 167 | return false; |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 168 | } |
Lee Leahy | a444753 | 2017-03-09 10:45:02 -0800 | [diff] [blame] | 169 | udelay(100); |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 170 | } |
| 171 | return true; |
| 172 | } |
| 173 | |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 174 | asmlinkage void car_stage_entry(void) |
| 175 | { |
Aaron Durbin | eebe0e0 | 2016-03-18 11:19:38 -0500 | [diff] [blame] | 176 | struct postcar_frame pcf; |
Andrey Petrov | f748f83 | 2016-04-23 13:15:51 -0700 | [diff] [blame] | 177 | uintptr_t top_of_ram; |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 178 | bool s3wake; |
Ravi Sarawadi | 2da008a | 2016-04-27 15:20:14 -0700 | [diff] [blame] | 179 | struct chipset_power_state *ps = car_get_var_ptr(&power_state); |
Brandon Breitenstein | 135eae9 | 2016-09-30 13:57:12 -0700 | [diff] [blame] | 180 | void *smm_base; |
Andrey Petrov | 96e9ff1 | 2016-11-04 16:18:30 -0700 | [diff] [blame] | 181 | size_t smm_size, var_size; |
| 182 | const void *new_var_data; |
Brandon Breitenstein | 135eae9 | 2016-09-30 13:57:12 -0700 | [diff] [blame] | 183 | uintptr_t tseg_base; |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 184 | |
Alexandru Gagniuc | eaa0a17 | 2016-05-16 16:56:28 -0700 | [diff] [blame] | 185 | timestamp_add_now(TS_START_ROMSTAGE); |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 186 | |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 187 | soc_early_romstage_init(); |
Aaron Durbin | 108cd0e | 2016-04-11 15:01:58 -0500 | [diff] [blame] | 188 | disable_watchdog(); |
| 189 | |
Alexandru Gagniuc | 766ba77 | 2016-05-16 16:52:54 -0700 | [diff] [blame] | 190 | console_init(); |
| 191 | |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 192 | s3wake = fill_power_state(ps) == ACPI_S3; |
Lee Leahy | 9671faa | 2016-07-24 18:18:52 -0700 | [diff] [blame] | 193 | fsp_memory_init(s3wake); |
Shaunak Saha | a012254 | 2016-10-10 12:34:28 -0700 | [diff] [blame] | 194 | |
| 195 | if (punit_init()) |
| 196 | set_max_freq(); |
| 197 | else |
| 198 | printk(BIOS_DEBUG, "Punit failed to initialize properly\n"); |
| 199 | |
Andrey Petrov | 96e9ff1 | 2016-11-04 16:18:30 -0700 | [diff] [blame] | 200 | /* Stash variable MRC data and let cache system update it later */ |
| 201 | new_var_data = fsp_find_extension_hob_by_guid(hob_variable_guid, |
| 202 | &var_size); |
| 203 | if (new_var_data) |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 204 | mrc_cache_stash_data(MRC_VARIABLE_DATA, |
| 205 | car_get_var(fsp_version), new_var_data, |
| 206 | var_size); |
Andrey Petrov | 96e9ff1 | 2016-11-04 16:18:30 -0700 | [diff] [blame] | 207 | else |
| 208 | printk(BIOS_ERR, "Failed to determine variable data\n"); |
| 209 | |
Aaron Durbin | eebe0e0 | 2016-03-18 11:19:38 -0500 | [diff] [blame] | 210 | if (postcar_frame_init(&pcf, 1*KiB)) |
| 211 | die("Unable to initialize postcar frame.\n"); |
| 212 | |
Ravi Sarawadi | 15f6f3a | 2016-08-18 13:31:29 -0700 | [diff] [blame] | 213 | mainboard_save_dimm_info(); |
| 214 | |
Andrey Petrov | f748f83 | 2016-04-23 13:15:51 -0700 | [diff] [blame] | 215 | /* |
| 216 | * We need to make sure ramstage will be run cached. At this point exact |
| 217 | * location of ramstage in cbmem is not known. Instruct postcar to cache |
| 218 | * 16 megs under cbmem top which is a safe bet to cover ramstage. |
| 219 | */ |
| 220 | top_of_ram = (uintptr_t) cbmem_top(); |
| 221 | /* cbmem_top() needs to be at least 16 MiB aligned */ |
| 222 | assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram); |
Lee Leahy | 07441b5 | 2017-03-09 10:59:25 -0800 | [diff] [blame] | 223 | postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, |
| 224 | MTRR_TYPE_WRBACK); |
Andrey Petrov | f748f83 | 2016-04-23 13:15:51 -0700 | [diff] [blame] | 225 | |
Aaron Durbin | dfe614f | 2016-09-16 11:15:49 -0500 | [diff] [blame] | 226 | /* Cache the memory-mapped boot media. */ |
| 227 | if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)) |
| 228 | postcar_frame_add_mtrr(&pcf, -CONFIG_ROM_SIZE, CONFIG_ROM_SIZE, |
| 229 | MTRR_TYPE_WRPROT); |
| 230 | |
Brandon Breitenstein | 135eae9 | 2016-09-30 13:57:12 -0700 | [diff] [blame] | 231 | /* |
| 232 | * Cache the TSEG region at the top of ram. This region is |
| 233 | * not restricted to SMM mode until SMM has been relocated. |
| 234 | * By setting the region to cacheable it provides faster access |
| 235 | * when relocating the SMM handler as well as using the TSEG |
| 236 | * region for other purposes. |
| 237 | */ |
| 238 | smm_region(&smm_base, &smm_size); |
| 239 | tseg_base = (uintptr_t)smm_base; |
| 240 | postcar_frame_add_mtrr(&pcf, tseg_base, smm_size, MTRR_TYPE_WRBACK); |
| 241 | |
Aaron Durbin | eebe0e0 | 2016-03-18 11:19:38 -0500 | [diff] [blame] | 242 | run_postcar_phase(&pcf); |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 243 | } |
| 244 | |
Brandon Breitenstein | c31ba0e | 2016-07-27 17:34:45 -0700 | [diff] [blame] | 245 | static void fill_console_params(FSPM_UPD *mupd) |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 246 | { |
| 247 | if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) { |
Lee Leahy | 07441b5 | 2017-03-09 10:59:25 -0800 | [diff] [blame] | 248 | mupd->FspmConfig.SerialDebugPortDevice = |
| 249 | CONFIG_UART_FOR_CONSOLE; |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 250 | /* use MMIO port type */ |
| 251 | mupd->FspmConfig.SerialDebugPortType = 2; |
| 252 | /* use 4 byte register stride */ |
| 253 | mupd->FspmConfig.SerialDebugPortStrideSize = 2; |
| 254 | /* used only for port type set to external */ |
| 255 | mupd->FspmConfig.SerialDebugPortAddress = 0; |
| 256 | } else { |
| 257 | mupd->FspmConfig.SerialDebugPortType = 0; |
| 258 | } |
| 259 | } |
| 260 | |
Andrey Petrov | f796c6e | 2016-11-18 14:57:51 -0800 | [diff] [blame] | 261 | void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 262 | { |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 263 | struct region_device rdev; |
Andrey Petrov | 96e9ff1 | 2016-11-04 16:18:30 -0700 | [diff] [blame] | 264 | |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 265 | fill_console_params(mupd); |
| 266 | mainboard_memory_init_params(mupd); |
| 267 | |
| 268 | /* Do NOT let FSP do any GPIO pad configuration */ |
Bora Guvendik | de4b09f | 2016-05-09 17:18:26 -0700 | [diff] [blame] | 269 | mupd->FspmConfig.PreMemGpioTablePtr = (uintptr_t) NULL; |
Andrey Petrov | 24a594f | 2016-06-28 17:37:09 -0700 | [diff] [blame] | 270 | |
| 271 | /* |
| 272 | * Tell CSE we do not need to use Ring Buffer Protocol (RBP) to fetch |
| 273 | * firmware for us if we are using memory-mapped SPI. This lets CSE |
| 274 | * state machine transition to next boot state, so that it can function |
| 275 | * as designed. |
| 276 | */ |
Aaron Durbin | 16c173f | 2016-08-11 14:04:10 -0500 | [diff] [blame] | 277 | mupd->FspmConfig.SkipCseRbp = |
| 278 | IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED); |
Andrey Petrov | 0910f4e | 2016-10-03 16:05:20 -0700 | [diff] [blame] | 279 | |
| 280 | /* |
| 281 | * Converged Security Engine (CSE) has secure storage functionality. |
| 282 | * HECI2 device can be used to access that functionality. However, part |
| 283 | * of S3 resume flow involves resetting HECI2 which takes 136ms. Since |
| 284 | * coreboot does not use secure storage functionality, instruct FSP to |
| 285 | * skip HECI2 reset. |
| 286 | */ |
| 287 | mupd->FspmConfig.EnableS3Heci2 = 0; |
Andrey Petrov | 96e9ff1 | 2016-11-04 16:18:30 -0700 | [diff] [blame] | 288 | |
| 289 | /* |
| 290 | * Apollolake splits MRC cache into two parts: constant and variable. |
| 291 | * The constant part is not expected to change often and variable is. |
| 292 | * Currently variable part consists of parameters that change on cold |
| 293 | * boots such as scrambler seed and some memory controller registers. |
| 294 | * Scrambler seed is vital for S3 resume case because attempt to use |
| 295 | * wrong/missing key renders DRAM contents useless. |
| 296 | */ |
| 297 | |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 298 | if (mrc_cache_get_current(MRC_VARIABLE_DATA, version, &rdev) == 0) { |
| 299 | /* Assume leaking is ok. */ |
| 300 | assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)); |
| 301 | mupd->FspmConfig.VariableNvsBufferPtr = rdev_mmap_full(&rdev); |
Andrey Petrov | 96e9ff1 | 2016-11-04 16:18:30 -0700 | [diff] [blame] | 302 | } |
| 303 | |
| 304 | car_set_var(fsp_version, version); |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 305 | } |
| 306 | |
| 307 | __attribute__ ((weak)) |
Brandon Breitenstein | c31ba0e | 2016-07-27 17:34:45 -0700 | [diff] [blame] | 308 | void mainboard_memory_init_params(FSPM_UPD *mupd) |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 309 | { |
| 310 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 311 | } |
Furquan Shaikh | bae6383 | 2016-06-17 15:50:24 -0700 | [diff] [blame] | 312 | |
Ravi Sarawadi | 15f6f3a | 2016-08-18 13:31:29 -0700 | [diff] [blame] | 313 | __attribute__ ((weak)) |
| 314 | void mainboard_save_dimm_info(void) |
| 315 | { |
| 316 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 317 | } |
| 318 | |
Furquan Shaikh | bae6383 | 2016-06-17 15:50:24 -0700 | [diff] [blame] | 319 | int get_sw_write_protect_state(void) |
| 320 | { |
| 321 | uint8_t status; |
Aaron Durbin | dfcc60c | 2016-12-14 12:32:35 -0600 | [diff] [blame] | 322 | const struct spi_flash *flash; |
Furquan Shaikh | d6c5559 | 2016-11-21 12:41:20 -0800 | [diff] [blame] | 323 | |
Aaron Durbin | dfcc60c | 2016-12-14 12:32:35 -0600 | [diff] [blame] | 324 | flash = boot_device_spi_flash(); |
Furquan Shaikh | d6c5559 | 2016-11-21 12:41:20 -0800 | [diff] [blame] | 325 | if (!flash) |
| 326 | return 0; |
Furquan Shaikh | bae6383 | 2016-06-17 15:50:24 -0700 | [diff] [blame] | 327 | |
| 328 | /* Return unprotected status if status read fails. */ |
Furquan Shaikh | d6c5559 | 2016-11-21 12:41:20 -0800 | [diff] [blame] | 329 | return spi_flash_status(flash, &status) ? 0 : !!(status & 0x80); |
Furquan Shaikh | bae6383 | 2016-06-17 15:50:24 -0700 | [diff] [blame] | 330 | } |