Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 1 | config SOC_INTEL_APOLLOLAKE |
| 2 | bool |
| 3 | help |
| 4 | Intel Apollolake support |
| 5 | |
| 6 | if SOC_INTEL_APOLLOLAKE |
| 7 | |
| 8 | config CPU_SPECIFIC_OPTIONS |
| 9 | def_bool y |
Aaron Durbin | ed35b7c | 2016-07-13 23:17:38 -0500 | [diff] [blame] | 10 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 11 | select ARCH_BOOTBLOCK_X86_32 |
| 12 | select ARCH_RAMSTAGE_X86_32 |
| 13 | select ARCH_ROMSTAGE_X86_32 |
| 14 | select ARCH_VERSTAGE_X86_32 |
Aaron Durbin | a9e03a3 | 2016-09-16 19:25:43 -0500 | [diff] [blame] | 15 | select BOOTBLOCK_CONSOLE |
Aaron Durbin | 7b2c781 | 2016-08-11 23:51:42 -0500 | [diff] [blame] | 16 | select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH |
Aaron Durbin | e8e118d | 2016-08-12 15:00:10 -0500 | [diff] [blame] | 17 | select BOOT_DEVICE_SUPPORTS_WRITES |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 18 | # CPU specific options |
| 19 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
| 20 | select IOAPIC |
| 21 | select SMP |
| 22 | select SSE2 |
| 23 | select SUPPORT_CPU_UCODE_IN_CBFS |
Saurabh Satija | 734aa87 | 2016-06-21 14:22:16 -0700 | [diff] [blame] | 24 | # Audio options |
| 25 | select ACPI_NHLT |
| 26 | select SOC_INTEL_COMMON_NHLT |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 27 | # Misc options |
Alexandru Gagniuc | dfc2b31 | 2015-10-06 17:16:41 -0700 | [diff] [blame] | 28 | select C_ENVIRONMENT_BOOTBLOCK |
Brandon Breitenstein | 135eae9 | 2016-09-30 13:57:12 -0700 | [diff] [blame] | 29 | select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 30 | select COLLECT_TIMESTAMPS |
Aaron Durbin | c3ee3f6 | 2016-05-11 10:35:49 -0500 | [diff] [blame] | 31 | select COMMON_FADT |
Duncan Laurie | d25dd99 | 2016-06-29 10:47:48 -0700 | [diff] [blame] | 32 | select GENERIC_GPIO_LIB |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 33 | select HAVE_INTEL_FIRMWARE |
Hannah Williams | d9c84ca | 2016-05-13 00:47:14 -0700 | [diff] [blame] | 34 | select HAVE_SMI_HANDLER |
Furquan Shaikh | ffb3a2d | 2016-10-24 15:28:23 -0700 | [diff] [blame] | 35 | select MRC_SETTINGS_PROTECT |
Aaron Durbin | f5ff854 | 2016-05-05 10:38:03 -0500 | [diff] [blame] | 36 | select NO_FIXED_XIP_ROM_SIZE |
Furquan Shaikh | 94b18a1 | 2016-05-04 23:25:16 -0700 | [diff] [blame] | 37 | select NO_XIP_EARLY_STAGES |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 38 | select PARALLEL_MP |
Andrey Petrov | a697c19 | 2016-12-07 10:47:46 -0800 | [diff] [blame] | 39 | select PARALLEL_MP_AP_WORK |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 40 | select PCIEXP_ASPM |
| 41 | select PCIEXP_COMMON_CLOCK |
| 42 | select PCIEXP_CLK_PM |
| 43 | select PCIEXP_L1_SUB_STATE |
Aaron Durbin | 79587ed | 2016-09-16 16:30:09 -0500 | [diff] [blame] | 44 | select POSTCAR_CONSOLE |
Aaron Durbin | eebe0e0 | 2016-03-18 11:19:38 -0500 | [diff] [blame] | 45 | select POSTCAR_STAGE |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 46 | select REG_SCRIPT |
| 47 | select RELOCATABLE_RAMSTAGE # Build fails if this is not selected |
Aaron Durbin | 16246ea | 2016-08-05 21:23:37 -0500 | [diff] [blame] | 48 | select RTC |
Hannah Williams | d9c84ca | 2016-05-13 00:47:14 -0700 | [diff] [blame] | 49 | select SMM_TSEG |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 50 | select SOC_INTEL_COMMON |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 51 | select SOC_INTEL_COMMON_ACPI |
Shaunak Saha | 60b4618 | 2016-08-02 17:25:13 -0700 | [diff] [blame] | 52 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
Duncan Laurie | ff8bce0 | 2016-06-27 10:57:13 -0700 | [diff] [blame] | 53 | select SOC_INTEL_COMMON_LPSS_I2C |
| 54 | select SOC_INTEL_COMMON_SMI |
Furquan Shaikh | d0c00052 | 2016-11-21 09:19:53 -0800 | [diff] [blame] | 55 | select SOC_INTEL_COMMON_SPI_FLASH_PROTECT |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 56 | select UDELAY_TSC |
Andrey Petrov | 87fb1a6 | 2016-02-10 17:47:03 -0800 | [diff] [blame] | 57 | select TSC_CONSTANT_RATE |
Hannah Williams | b13d454 | 2016-03-14 17:38:51 -0700 | [diff] [blame] | 58 | select TSC_MONOTONIC_TIMER |
| 59 | select HAVE_MONOTONIC_TIMER |
Andrey Petrov | 0d18791 | 2016-02-25 18:39:38 -0800 | [diff] [blame] | 60 | select PLATFORM_USES_FSP2_0 |
Zhao, Lijian | d8d42c2 | 2016-03-14 14:19:22 -0700 | [diff] [blame] | 61 | select HAVE_HARD_RESET |
| 62 | select SOC_INTEL_COMMON |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 63 | select SOC_INTEL_COMMON_GFX_OPREGION |
Andrey Petrov | d8db26d | 2017-03-06 14:47:05 -0800 | [diff] [blame] | 64 | select SOC_INTEL_COMMON_BLOCK |
| 65 | select SOC_INTEL_COMMON_BLOCK_CSE |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 66 | select ADD_VBT_DATA_FILE |
Zhao, Lijian | d8d42c2 | 2016-03-14 14:19:22 -0700 | [diff] [blame] | 67 | |
Furquan Shaikh | 87b1bcc | 2016-07-22 12:57:51 -0700 | [diff] [blame] | 68 | config CHROMEOS |
| 69 | select CHROMEOS_RAMOOPS_DYNAMIC |
Furquan Shaikh | 87b1bcc | 2016-07-22 12:57:51 -0700 | [diff] [blame] | 70 | select EC_SOFTWARE_SYNC if EC_GOOGLE_CHROMEEC |
| 71 | select SEPARATE_VERSTAGE |
| 72 | select VBOOT_OPROM_MATTERS |
Furquan Shaikh | 7c7b291 | 2016-07-22 09:02:35 -0700 | [diff] [blame] | 73 | select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT |
Furquan Shaikh | 87b1bcc | 2016-07-22 12:57:51 -0700 | [diff] [blame] | 74 | select VBOOT_STARTS_IN_BOOTBLOCK |
Furquan Shaikh | 2a12e2e | 2016-07-25 11:48:03 -0700 | [diff] [blame] | 75 | select VBOOT_VBNV_CMOS |
| 76 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
Furquan Shaikh | 87b1bcc | 2016-07-22 12:57:51 -0700 | [diff] [blame] | 77 | select VIRTUAL_DEV_SWITCH |
| 78 | |
Aaron Durbin | 80a3df2 | 2016-04-27 23:05:52 -0500 | [diff] [blame] | 79 | config TPM_ON_FAST_SPI |
| 80 | bool |
| 81 | default n |
| 82 | select LPC_TPM |
| 83 | help |
| 84 | TPM part is conntected on Fast SPI interface, but the LPC MMIO |
| 85 | TPM transactions are decoded and serialized over the SPI interface. |
| 86 | |
Zhao, Lijian | d8d42c2 | 2016-03-14 14:19:22 -0700 | [diff] [blame] | 87 | config SOC_INTEL_COMMON_RESET |
| 88 | bool |
Andrey Petrov | 9c0e180 | 2016-06-23 08:26:00 -0700 | [diff] [blame] | 89 | default y |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 90 | |
Alexandru Gagniuc | dfc2b31 | 2015-10-06 17:16:41 -0700 | [diff] [blame] | 91 | config MMCONF_BASE_ADDRESS |
| 92 | hex "PCI MMIO Base Address" |
| 93 | default 0xe0000000 |
| 94 | |
| 95 | config IOSF_BASE_ADDRESS |
| 96 | hex "MMIO Base Address of sideband bus" |
| 97 | default 0xd0000000 |
| 98 | |
| 99 | config DCACHE_RAM_BASE |
| 100 | hex "Base address of cache-as-RAM" |
| 101 | default 0xfef00000 |
| 102 | |
| 103 | config DCACHE_RAM_SIZE |
| 104 | hex "Length in bytes of cache-as-RAM" |
Andrey Petrov | 0dde291 | 2016-06-27 15:21:26 -0700 | [diff] [blame] | 105 | default 0xc0000 |
Alexandru Gagniuc | dfc2b31 | 2015-10-06 17:16:41 -0700 | [diff] [blame] | 106 | help |
| 107 | The size of the cache-as-ram region required during bootblock |
| 108 | and/or romstage. |
| 109 | |
| 110 | config DCACHE_BSP_STACK_SIZE |
| 111 | hex |
| 112 | default 0x4000 |
| 113 | help |
| 114 | The amount of anticipated stack usage in CAR by bootblock and |
| 115 | other stages. |
| 116 | |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 117 | config CPU_ADDR_BITS |
| 118 | int |
| 119 | default 36 |
| 120 | |
Duncan Laurie | ff8bce0 | 2016-06-27 10:57:13 -0700 | [diff] [blame] | 121 | config SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ |
| 122 | depends on SOC_INTEL_COMMON_LPSS_I2C |
| 123 | int |
| 124 | default 133 |
| 125 | |
Andrey Petrov | 87fb1a6 | 2016-02-10 17:47:03 -0800 | [diff] [blame] | 126 | config CONSOLE_UART_BASE_ADDRESS |
| 127 | depends on CONSOLE_SERIAL |
| 128 | hex "MMIO base address for UART" |
| 129 | default 0xde000000 |
| 130 | |
Aaron Durbin | 6181030 | 2016-02-24 18:49:07 -0600 | [diff] [blame] | 131 | config SOC_UART_DEBUG |
| 132 | bool "Enable SoC UART debug port selected by UART_FOR_CONSOLE." |
| 133 | default n |
| 134 | select CONSOLE_SERIAL |
Aaron Durbin | 6181030 | 2016-02-24 18:49:07 -0600 | [diff] [blame] | 135 | select DRIVERS_UART |
| 136 | select DRIVERS_UART_8250MEM_32 |
| 137 | select NO_UART_ON_SUPERIO |
| 138 | |
Aaron Durbin | ada13ed | 2016-02-11 14:47:33 -0600 | [diff] [blame] | 139 | # 32KiB bootblock is all that is mapped in by the CSE at top of 4GiB. |
| 140 | config C_ENV_BOOTBLOCK_SIZE |
| 141 | hex |
| 142 | default 0x8000 |
| 143 | |
Andrey Petrov | 5672dcd | 2016-02-12 15:12:43 -0800 | [diff] [blame] | 144 | # This SoC does not map SPI flash like many previous SoC. Therefore we provide |
| 145 | # a custom media driver that facilitates mapping |
| 146 | config X86_TOP4G_BOOTMEDIA_MAP |
| 147 | bool |
| 148 | default n |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 149 | |
| 150 | config ROMSTAGE_ADDR |
| 151 | hex |
Andrey Petrov | 7f72c9b | 2016-06-24 18:15:09 -0700 | [diff] [blame] | 152 | default 0xfef20000 |
Andrey Petrov | b483146 | 2016-02-25 17:42:25 -0800 | [diff] [blame] | 153 | help |
| 154 | The base address (in CAR) where romstage should be linked |
| 155 | |
Aaron Durbin | bef75e7 | 2016-05-26 11:00:44 -0500 | [diff] [blame] | 156 | config VERSTAGE_ADDR |
| 157 | hex |
Andrey Petrov | 7f72c9b | 2016-06-24 18:15:09 -0700 | [diff] [blame] | 158 | default 0xfef40000 |
Aaron Durbin | bef75e7 | 2016-05-26 11:00:44 -0500 | [diff] [blame] | 159 | help |
| 160 | The base address (in CAR) where verstage should be linked |
| 161 | |
Hannah Williams | b13d454 | 2016-03-14 17:38:51 -0700 | [diff] [blame] | 162 | config CACHE_MRC_SETTINGS |
| 163 | bool |
| 164 | default y |
| 165 | |
Andrey Petrov | 96e9ff1 | 2016-11-04 16:18:30 -0700 | [diff] [blame] | 166 | config MRC_SETTINGS_VARIABLE_DATA |
| 167 | bool |
| 168 | default y |
| 169 | |
Andrey Petrov | 79091db7 | 2016-05-17 00:03:27 -0700 | [diff] [blame] | 170 | config FSP_M_ADDR |
| 171 | hex |
Andrey Petrov | 7f72c9b | 2016-06-24 18:15:09 -0700 | [diff] [blame] | 172 | default 0xfef40000 |
Andrey Petrov | 79091db7 | 2016-05-17 00:03:27 -0700 | [diff] [blame] | 173 | help |
| 174 | The address FSP-M will be relocated to during build time |
| 175 | |
Aaron Durbin | 9f444c3 | 2016-05-20 10:48:44 -0500 | [diff] [blame] | 176 | config NEED_LBP2 |
| 177 | bool "Write contents for logical boot partition 2." |
| 178 | default n |
| 179 | help |
| 180 | Write the contents from a file into the logical boot partition 2 |
| 181 | region defined by LBP2_FMAP_NAME. |
| 182 | |
| 183 | config LBP2_FMAP_NAME |
| 184 | string "Name of FMAP region to put logical boot partition 2" |
| 185 | depends on NEED_LBP2 |
| 186 | default "SIGN_CSE" |
| 187 | help |
| 188 | Name of FMAP region to write logical boot partition 2 data. |
| 189 | |
| 190 | config LBP2_FILE_NAME |
| 191 | string "Path of file to write to logical boot partition 2 region" |
| 192 | depends on NEED_LBP2 |
| 193 | default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/lbp2.bin" |
| 194 | help |
| 195 | Name of file to store in the logical boot partition 2 region. |
| 196 | |
Furquan Shaikh | 7043bf3 | 2016-05-28 12:57:05 -0700 | [diff] [blame] | 197 | config NEED_IFWI |
| 198 | bool "Write content into IFWI region" |
| 199 | default n |
| 200 | help |
| 201 | Write the content from a file into IFWI region defined by |
| 202 | IFWI_FMAP_NAME. |
| 203 | |
| 204 | config IFWI_FMAP_NAME |
| 205 | string "Name of FMAP region to pull IFWI into" |
| 206 | depends on NEED_IFWI |
| 207 | default "IFWI" |
| 208 | help |
| 209 | Name of FMAP region to write IFWI. |
| 210 | |
| 211 | config IFWI_FILE_NAME |
| 212 | string "Path of file to write to IFWI region" |
| 213 | depends on NEED_IFWI |
| 214 | default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/ifwi.bin" |
| 215 | help |
| 216 | Name of file to store in the IFWI region. |
| 217 | |
Sathyanarayana Nujella | c446704 | 2016-10-26 17:38:49 -0700 | [diff] [blame] | 218 | config HEAP_SIZE |
| 219 | hex |
| 220 | default 0x8000 |
| 221 | |
Sathyanarayana Nujella | 3e0a3fb | 2016-10-26 17:31:36 -0700 | [diff] [blame] | 222 | config NHLT_DMIC_1CH_16B |
| 223 | bool |
| 224 | depends on ACPI_NHLT |
| 225 | default n |
| 226 | help |
| 227 | Include DSP firmware settings for 1 channel 16B DMIC array. |
| 228 | |
Saurabh Satija | 734aa87 | 2016-06-21 14:22:16 -0700 | [diff] [blame] | 229 | config NHLT_DMIC_2CH_16B |
| 230 | bool |
| 231 | depends on ACPI_NHLT |
| 232 | default n |
| 233 | help |
| 234 | Include DSP firmware settings for 2 channel 16B DMIC array. |
| 235 | |
Sathyanarayana Nujella | 3e0a3fb | 2016-10-26 17:31:36 -0700 | [diff] [blame] | 236 | config NHLT_DMIC_4CH_16B |
| 237 | bool |
| 238 | depends on ACPI_NHLT |
| 239 | default n |
| 240 | help |
| 241 | Include DSP firmware settings for 4 channel 16B DMIC array. |
| 242 | |
Saurabh Satija | 734aa87 | 2016-06-21 14:22:16 -0700 | [diff] [blame] | 243 | config NHLT_MAX98357 |
| 244 | bool |
| 245 | depends on ACPI_NHLT |
| 246 | default n |
| 247 | help |
| 248 | Include DSP firmware settings for headset codec. |
| 249 | |
| 250 | config NHLT_DA7219 |
| 251 | bool |
| 252 | depends on ACPI_NHLT |
| 253 | default n |
| 254 | help |
| 255 | Include DSP firmware settings for headset codec. |
Andrey Petrov | 3f4aece | 2016-06-27 13:39:34 -0700 | [diff] [blame] | 256 | choice |
| 257 | prompt "Cache-as-ram implementation" |
| 258 | default CAR_CQOS |
| 259 | help |
| 260 | This option allows you to select how cache-as-ram (CAR) is set up. |
| 261 | |
| 262 | config CAR_NEM |
| 263 | bool "Non-evict mode" |
| 264 | help |
| 265 | Traditionally, CAR is set up by using Non-Evict mode. This method |
| 266 | does not allow CAR and cache to co-exist, because cache fills are |
| 267 | block in NEM mode. |
| 268 | |
| 269 | config CAR_CQOS |
| 270 | bool "Cache Quality of Service" |
| 271 | help |
| 272 | Cache Quality of Service allows more fine-grained control of cache |
| 273 | usage. As result, it is possible to set up portion of L2 cache for |
| 274 | CAR and use remainder for actual caching. |
| 275 | |
| 276 | endchoice |
Saurabh Satija | 734aa87 | 2016-06-21 14:22:16 -0700 | [diff] [blame] | 277 | |
Aaron Durbin | bdb6cc9 | 2016-08-11 09:48:52 -0500 | [diff] [blame] | 278 | config SPI_FLASH_INCLUDE_ALL_DRIVERS |
| 279 | bool |
| 280 | default n |
| 281 | |
Brandon Breitenstein | 135eae9 | 2016-09-30 13:57:12 -0700 | [diff] [blame] | 282 | config SMM_RESERVED_SIZE |
| 283 | hex |
| 284 | default 0x100000 |
| 285 | |
Andrey Petrov | 4c5b31e | 2016-11-06 23:43:57 -0800 | [diff] [blame] | 286 | config IFD_CHIPSET |
| 287 | string |
| 288 | default "aplk" |
| 289 | |
Alexandru Gagniuc | 7e86cd4 | 2015-10-06 10:33:49 -0700 | [diff] [blame] | 290 | endif |