Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 5 | * Copyright (C) 2015 Intel Corp. |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
Patrick Georgi | 25509ee | 2015-03-26 15:17:45 +0100 | [diff] [blame] | 18 | * Foundation, Inc. |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 19 | */ |
| 20 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 21 | #include <chip.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 22 | #include <console/console.h> |
| 23 | #include <device/device.h> |
| 24 | #include <device/pci.h> |
Aaron Durbin | 789f2b6 | 2015-09-09 17:05:06 -0500 | [diff] [blame] | 25 | #include <fsp/util.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 26 | #include <soc/pci_devs.h> |
| 27 | #include <soc/ramstage.h> |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 28 | |
| 29 | static void pci_domain_set_resources(device_t dev) |
| 30 | { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 31 | printk(BIOS_SPEW, "%s/%s ( %s )\n", |
| 32 | __FILE__, __func__, dev_name(dev)); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 33 | assign_resources(dev->link_list); |
| 34 | } |
| 35 | |
| 36 | static struct device_operations pci_domain_ops = { |
| 37 | .read_resources = pci_domain_read_resources, |
| 38 | .set_resources = pci_domain_set_resources, |
| 39 | .enable_resources = NULL, |
| 40 | .init = NULL, |
| 41 | .scan_bus = pci_domain_scan_bus, |
| 42 | .ops_pci_bus = pci_bus_default_ops, |
| 43 | }; |
| 44 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 45 | static void cpu_bus_noop(device_t dev) { } |
| 46 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 47 | static struct device_operations cpu_bus_ops = { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 48 | .read_resources = cpu_bus_noop, |
| 49 | .set_resources = cpu_bus_noop, |
| 50 | .enable_resources = cpu_bus_noop, |
| 51 | .init = soc_init_cpus |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 52 | }; |
| 53 | |
| 54 | |
| 55 | static void enable_dev(device_t dev) |
| 56 | { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 57 | printk(BIOS_SPEW, "----------\n%s/%s ( %s ), type: %d\n", |
| 58 | __FILE__, __func__, |
| 59 | dev_name(dev), dev->path.type); |
| 60 | printk(BIOS_SPEW, "vendor: 0x%04x. device: 0x%04x\n", |
| 61 | pci_read_config16(dev, PCI_VENDOR_ID), |
| 62 | pci_read_config16(dev, PCI_DEVICE_ID)); |
| 63 | printk(BIOS_SPEW, "class: 0x%02x %s\n" |
| 64 | "subclass: 0x%02x %s\n" |
| 65 | "prog: 0x%02x\n" |
| 66 | "revision: 0x%02x\n", |
| 67 | pci_read_config16(dev, PCI_CLASS_DEVICE) >> 8, |
| 68 | get_pci_class_name(dev), |
| 69 | pci_read_config16(dev, PCI_CLASS_DEVICE) & 0xff, |
| 70 | get_pci_subclass_name(dev), |
| 71 | pci_read_config8(dev, PCI_CLASS_PROG), |
| 72 | pci_read_config8(dev, PCI_REVISION_ID)); |
| 73 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 74 | /* Set the operations if it is a special bus type */ |
| 75 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
| 76 | dev->ops = &pci_domain_ops; |
| 77 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
| 78 | dev->ops = &cpu_bus_ops; |
| 79 | } else if (dev->path.type == DEVICE_PATH_PCI) { |
| 80 | /* Handle south cluster enablement. */ |
| 81 | if (PCI_SLOT(dev->path.pci.devfn) > GFX_DEV && |
| 82 | (dev->ops == NULL || dev->ops->enable == NULL)) { |
| 83 | southcluster_enable_dev(dev); |
| 84 | } |
| 85 | } |
| 86 | } |
| 87 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 88 | void soc_silicon_init_params(SILICON_INIT_UPD *params) |
| 89 | { |
| 90 | device_t dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); |
| 91 | struct soc_intel_braswell_config *config = dev->chip_info; |
| 92 | |
| 93 | /* Set the parameters for SiliconInit */ |
| 94 | printk(BIOS_DEBUG, "Updating UPD values for SiliconInit\n"); |
| 95 | params->PcdSdcardMode = config->PcdSdcardMode; |
| 96 | params->PcdEnableHsuart0 = config->PcdEnableHsuart0; |
| 97 | params->PcdEnableHsuart1 = config->PcdEnableHsuart1; |
| 98 | params->PcdEnableAzalia = config->PcdEnableAzalia; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 99 | params->PcdEnableSata = config->PcdEnableSata; |
| 100 | params->PcdEnableXhci = config->PcdEnableXhci; |
| 101 | params->PcdEnableLpe = config->PcdEnableLpe; |
| 102 | params->PcdEnableDma0 = config->PcdEnableDma0; |
| 103 | params->PcdEnableDma1 = config->PcdEnableDma1; |
| 104 | params->PcdEnableI2C0 = config->PcdEnableI2C0; |
| 105 | params->PcdEnableI2C1 = config->PcdEnableI2C1; |
| 106 | params->PcdEnableI2C2 = config->PcdEnableI2C2; |
| 107 | params->PcdEnableI2C3 = config->PcdEnableI2C3; |
| 108 | params->PcdEnableI2C4 = config->PcdEnableI2C4; |
| 109 | params->PcdEnableI2C5 = config->PcdEnableI2C5; |
| 110 | params->PcdEnableI2C6 = config->PcdEnableI2C6; |
Subrata Banik | 13cd331 | 2015-08-07 18:22:54 +0530 | [diff] [blame] | 111 | params->GraphicsConfigPtr = 0; |
| 112 | params->AzaliaConfigPtr = 0; |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 113 | params->PunitPwrConfigDisable = config->PunitPwrConfigDisable; |
| 114 | params->ChvSvidConfig = config->ChvSvidConfig; |
| 115 | params->DptfDisable = config->DptfDisable; |
| 116 | params->PcdEmmcMode = config->PcdEmmcMode; |
| 117 | params->PcdUsb3ClkSsc = config->PcdUsb3ClkSsc; |
| 118 | params->PcdDispClkSsc = config->PcdDispClkSsc; |
| 119 | params->PcdSataClkSsc = config->PcdSataClkSsc; |
| 120 | params->Usb2Port0PerPortPeTxiSet = config->Usb2Port0PerPortPeTxiSet; |
| 121 | params->Usb2Port0PerPortTxiSet = config->Usb2Port0PerPortTxiSet; |
| 122 | params->Usb2Port0IUsbTxEmphasisEn = config->Usb2Port0IUsbTxEmphasisEn; |
| 123 | params->Usb2Port0PerPortTxPeHalf = config->Usb2Port0PerPortTxPeHalf; |
| 124 | params->Usb2Port1PerPortPeTxiSet = config->Usb2Port1PerPortPeTxiSet; |
| 125 | params->Usb2Port1PerPortTxiSet = config->Usb2Port1PerPortTxiSet; |
| 126 | params->Usb2Port1IUsbTxEmphasisEn = config->Usb2Port1IUsbTxEmphasisEn; |
| 127 | params->Usb2Port1PerPortTxPeHalf = config->Usb2Port1PerPortTxPeHalf; |
| 128 | params->Usb2Port2PerPortPeTxiSet = config->Usb2Port2PerPortPeTxiSet; |
| 129 | params->Usb2Port2PerPortTxiSet = config->Usb2Port2PerPortTxiSet; |
| 130 | params->Usb2Port2IUsbTxEmphasisEn = config->Usb2Port2IUsbTxEmphasisEn; |
| 131 | params->Usb2Port2PerPortTxPeHalf = config->Usb2Port2PerPortTxPeHalf; |
| 132 | params->Usb2Port3PerPortPeTxiSet = config->Usb2Port3PerPortPeTxiSet; |
| 133 | params->Usb2Port3PerPortTxiSet = config->Usb2Port3PerPortTxiSet; |
| 134 | params->Usb2Port3IUsbTxEmphasisEn = config->Usb2Port3IUsbTxEmphasisEn; |
| 135 | params->Usb2Port3PerPortTxPeHalf = config->Usb2Port3PerPortTxPeHalf; |
| 136 | params->Usb2Port4PerPortPeTxiSet = config->Usb2Port4PerPortPeTxiSet; |
| 137 | params->Usb2Port4PerPortTxiSet = config->Usb2Port4PerPortTxiSet; |
| 138 | params->Usb2Port4IUsbTxEmphasisEn = config->Usb2Port4IUsbTxEmphasisEn; |
| 139 | params->Usb2Port4PerPortTxPeHalf = config->Usb2Port4PerPortTxPeHalf; |
| 140 | params->Usb3Lane0Ow2tapgen2deemph3p5 = |
| 141 | config->Usb3Lane0Ow2tapgen2deemph3p5; |
| 142 | params->Usb3Lane1Ow2tapgen2deemph3p5 = |
| 143 | config->Usb3Lane1Ow2tapgen2deemph3p5; |
| 144 | params->Usb3Lane2Ow2tapgen2deemph3p5 = |
| 145 | config->Usb3Lane2Ow2tapgen2deemph3p5; |
| 146 | params->Usb3Lane3Ow2tapgen2deemph3p5 = |
| 147 | config->Usb3Lane3Ow2tapgen2deemph3p5; |
| 148 | params->PcdSataInterfaceSpeed = config->PcdSataInterfaceSpeed; |
| 149 | params->PcdPchUsbSsicPort = config->PcdPchUsbSsicPort; |
| 150 | params->PcdPchUsbHsicPort = config->PcdPchUsbHsicPort; |
| 151 | params->PcdPcieRootPortSpeed = config->PcdPcieRootPortSpeed; |
| 152 | params->PcdPchSsicEnable = config->PcdPchSsicEnable; |
| 153 | params->PcdLogoPtr = config->PcdLogoPtr; |
| 154 | params->PcdLogoSize = config->PcdLogoSize; |
| 155 | params->PcdRtcLock = config->PcdRtcLock; |
| 156 | params->PMIC_I2CBus = config->PMIC_I2CBus; |
| 157 | params->ISPEnable = config->ISPEnable; |
| 158 | params->ISPPciDevConfig = config->ISPPciDevConfig; |
| 159 | } |
| 160 | |
| 161 | void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, |
| 162 | SILICON_INIT_UPD *new) |
| 163 | { |
| 164 | /* Display the parameters for SiliconInit */ |
| 165 | printk(BIOS_SPEW, "UPD values for SiliconInit:\n"); |
| 166 | soc_display_upd_value("PcdSdcardMode", 1, old->PcdSdcardMode, |
| 167 | new->PcdSdcardMode); |
| 168 | soc_display_upd_value("PcdEnableHsuart0", 1, old->PcdEnableHsuart0, |
| 169 | new->PcdEnableHsuart0); |
| 170 | soc_display_upd_value("PcdEnableHsuart1", 1, old->PcdEnableHsuart1, |
| 171 | new->PcdEnableHsuart1); |
| 172 | soc_display_upd_value("PcdEnableAzalia", 1, old->PcdEnableAzalia, |
| 173 | new->PcdEnableAzalia); |
Subrata Banik | 13cd331 | 2015-08-07 18:22:54 +0530 | [diff] [blame] | 174 | soc_display_upd_value("AzaliaConfigPtr", 4, |
| 175 | (uint32_t)old->AzaliaConfigPtr, |
| 176 | (uint32_t)new->AzaliaConfigPtr); |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 177 | soc_display_upd_value("PcdEnableSata", 1, old->PcdEnableSata, |
| 178 | new->PcdEnableSata); |
| 179 | soc_display_upd_value("PcdEnableXhci", 1, old->PcdEnableXhci, |
| 180 | new->PcdEnableXhci); |
| 181 | soc_display_upd_value("PcdEnableLpe", 1, old->PcdEnableLpe, |
| 182 | new->PcdEnableLpe); |
| 183 | soc_display_upd_value("PcdEnableDma0", 1, old->PcdEnableDma0, |
| 184 | new->PcdEnableDma0); |
| 185 | soc_display_upd_value("PcdEnableDma1", 1, old->PcdEnableDma1, |
| 186 | new->PcdEnableDma1); |
| 187 | soc_display_upd_value("PcdEnableI2C0", 1, old->PcdEnableI2C0, |
| 188 | new->PcdEnableI2C0); |
| 189 | soc_display_upd_value("PcdEnableI2C1", 1, old->PcdEnableI2C1, |
| 190 | new->PcdEnableI2C1); |
| 191 | soc_display_upd_value("PcdEnableI2C2", 1, old->PcdEnableI2C2, |
| 192 | new->PcdEnableI2C2); |
| 193 | soc_display_upd_value("PcdEnableI2C3", 1, old->PcdEnableI2C3, |
| 194 | new->PcdEnableI2C3); |
| 195 | soc_display_upd_value("PcdEnableI2C4", 1, old->PcdEnableI2C4, |
| 196 | new->PcdEnableI2C4); |
| 197 | soc_display_upd_value("PcdEnableI2C5", 1, old->PcdEnableI2C5, |
| 198 | new->PcdEnableI2C5); |
| 199 | soc_display_upd_value("PcdEnableI2C6", 1, old->PcdEnableI2C6, |
| 200 | new->PcdEnableI2C6); |
| 201 | soc_display_upd_value("PcdGraphicsConfigPtr", 4, |
Subrata Banik | 13cd331 | 2015-08-07 18:22:54 +0530 | [diff] [blame] | 202 | old->GraphicsConfigPtr, new->GraphicsConfigPtr); |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 203 | soc_display_upd_value("GpioFamilyInitTablePtr", 4, |
| 204 | (uint32_t)old->GpioFamilyInitTablePtr, |
| 205 | (uint32_t)new->GpioFamilyInitTablePtr); |
| 206 | soc_display_upd_value("GpioPadInitTablePtr", 4, |
| 207 | (uint32_t)old->GpioPadInitTablePtr, |
| 208 | (uint32_t)new->GpioPadInitTablePtr); |
| 209 | soc_display_upd_value("PunitPwrConfigDisable", 1, |
| 210 | old->PunitPwrConfigDisable, |
| 211 | new->PunitPwrConfigDisable); |
| 212 | soc_display_upd_value("ChvSvidConfig", 1, old->ChvSvidConfig, |
| 213 | new->ChvSvidConfig); |
| 214 | soc_display_upd_value("DptfDisable", 1, old->DptfDisable, |
| 215 | new->DptfDisable); |
| 216 | soc_display_upd_value("PcdEmmcMode", 1, old->PcdEmmcMode, |
| 217 | new->PcdEmmcMode); |
| 218 | soc_display_upd_value("PcdUsb3ClkSsc", 1, old->PcdUsb3ClkSsc, |
| 219 | new->PcdUsb3ClkSsc); |
| 220 | soc_display_upd_value("PcdDispClkSsc", 1, old->PcdDispClkSsc, |
| 221 | new->PcdDispClkSsc); |
| 222 | soc_display_upd_value("PcdSataClkSsc", 1, old->PcdSataClkSsc, |
| 223 | new->PcdSataClkSsc); |
| 224 | soc_display_upd_value("Usb2Port0PerPortPeTxiSet", 1, |
| 225 | old->Usb2Port0PerPortPeTxiSet, |
| 226 | new->Usb2Port0PerPortPeTxiSet); |
| 227 | soc_display_upd_value("Usb2Port0PerPortTxiSet", 1, |
| 228 | old->Usb2Port0PerPortTxiSet, |
| 229 | new->Usb2Port0PerPortTxiSet); |
| 230 | soc_display_upd_value("Usb2Port0IUsbTxEmphasisEn", 1, |
| 231 | old->Usb2Port0IUsbTxEmphasisEn, |
| 232 | new->Usb2Port0IUsbTxEmphasisEn); |
| 233 | soc_display_upd_value("Usb2Port0PerPortTxPeHalf", 1, |
| 234 | old->Usb2Port0PerPortTxPeHalf, |
| 235 | new->Usb2Port0PerPortTxPeHalf); |
| 236 | soc_display_upd_value("Usb2Port1PerPortPeTxiSet", 1, |
| 237 | old->Usb2Port1PerPortPeTxiSet, |
| 238 | new->Usb2Port1PerPortPeTxiSet); |
| 239 | soc_display_upd_value("Usb2Port1PerPortTxiSet", 1, |
| 240 | old->Usb2Port1PerPortTxiSet, |
| 241 | new->Usb2Port1PerPortTxiSet); |
| 242 | soc_display_upd_value("Usb2Port1IUsbTxEmphasisEn", 1, |
| 243 | old->Usb2Port1IUsbTxEmphasisEn, |
| 244 | new->Usb2Port1IUsbTxEmphasisEn); |
| 245 | soc_display_upd_value("Usb2Port1PerPortTxPeHalf", 1, |
| 246 | old->Usb2Port1PerPortTxPeHalf, |
| 247 | new->Usb2Port1PerPortTxPeHalf); |
| 248 | soc_display_upd_value("Usb2Port2PerPortPeTxiSet", 1, |
| 249 | old->Usb2Port2PerPortPeTxiSet, |
| 250 | new->Usb2Port2PerPortPeTxiSet); |
| 251 | soc_display_upd_value("Usb2Port2PerPortTxiSet", 1, |
| 252 | old->Usb2Port2PerPortTxiSet, |
| 253 | new->Usb2Port2PerPortTxiSet); |
| 254 | soc_display_upd_value("Usb2Port2IUsbTxEmphasisEn", 1, |
| 255 | old->Usb2Port2IUsbTxEmphasisEn, |
| 256 | new->Usb2Port2IUsbTxEmphasisEn); |
| 257 | soc_display_upd_value("Usb2Port2PerPortTxPeHalf", 1, |
| 258 | old->Usb2Port2PerPortTxPeHalf, |
| 259 | new->Usb2Port2PerPortTxPeHalf); |
| 260 | soc_display_upd_value("Usb2Port3PerPortPeTxiSet", 1, |
| 261 | old->Usb2Port3PerPortPeTxiSet, |
| 262 | new->Usb2Port3PerPortPeTxiSet); |
| 263 | soc_display_upd_value("Usb2Port3PerPortTxiSet", 1, |
| 264 | old->Usb2Port3PerPortTxiSet, |
| 265 | new->Usb2Port3PerPortTxiSet); |
| 266 | soc_display_upd_value("Usb2Port3IUsbTxEmphasisEn", 1, |
| 267 | old->Usb2Port3IUsbTxEmphasisEn, |
| 268 | new->Usb2Port3IUsbTxEmphasisEn); |
| 269 | soc_display_upd_value("Usb2Port3PerPortTxPeHalf", 1, |
| 270 | old->Usb2Port3PerPortTxPeHalf, |
| 271 | new->Usb2Port3PerPortTxPeHalf); |
| 272 | soc_display_upd_value("Usb2Port4PerPortPeTxiSet", 1, |
| 273 | old->Usb2Port4PerPortPeTxiSet, |
| 274 | new->Usb2Port4PerPortPeTxiSet); |
| 275 | soc_display_upd_value("Usb2Port4PerPortTxiSet", 1, |
| 276 | old->Usb2Port4PerPortTxiSet, |
| 277 | new->Usb2Port4PerPortTxiSet); |
| 278 | soc_display_upd_value("Usb2Port4IUsbTxEmphasisEn", 1, |
| 279 | old->Usb2Port4IUsbTxEmphasisEn, |
| 280 | new->Usb2Port4IUsbTxEmphasisEn); |
| 281 | soc_display_upd_value("Usb2Port4PerPortTxPeHalf", 1, |
| 282 | old->Usb2Port4PerPortTxPeHalf, |
| 283 | new->Usb2Port4PerPortTxPeHalf); |
| 284 | soc_display_upd_value("Usb3Lane0Ow2tapgen2deemph3p5", 1, |
| 285 | old->Usb3Lane0Ow2tapgen2deemph3p5, |
| 286 | new->Usb3Lane0Ow2tapgen2deemph3p5); |
| 287 | soc_display_upd_value("Usb3Lane1Ow2tapgen2deemph3p5", 1, |
| 288 | old->Usb3Lane1Ow2tapgen2deemph3p5, |
| 289 | new->Usb3Lane1Ow2tapgen2deemph3p5); |
| 290 | soc_display_upd_value("Usb3Lane2Ow2tapgen2deemph3p5", 1, |
| 291 | old->Usb3Lane2Ow2tapgen2deemph3p5, |
| 292 | new->Usb3Lane2Ow2tapgen2deemph3p5); |
| 293 | soc_display_upd_value("Usb3Lane3Ow2tapgen2deemph3p5", 1, |
| 294 | old->Usb3Lane3Ow2tapgen2deemph3p5, |
| 295 | new->Usb3Lane3Ow2tapgen2deemph3p5); |
| 296 | soc_display_upd_value("PcdSataInterfaceSpeed", 1, |
| 297 | old->PcdSataInterfaceSpeed, |
| 298 | new->PcdSataInterfaceSpeed); |
| 299 | soc_display_upd_value("PcdPchUsbSsicPort", 1, |
| 300 | old->PcdPchUsbSsicPort, new->PcdPchUsbSsicPort); |
| 301 | soc_display_upd_value("PcdPchUsbHsicPort", 1, |
| 302 | old->PcdPchUsbHsicPort, new->PcdPchUsbHsicPort); |
| 303 | soc_display_upd_value("PcdPcieRootPortSpeed", 1, |
| 304 | old->PcdPcieRootPortSpeed, new->PcdPcieRootPortSpeed); |
| 305 | soc_display_upd_value("PcdPchSsicEnable", 1, old->PcdPchSsicEnable, |
| 306 | new->PcdPchSsicEnable); |
| 307 | soc_display_upd_value("PcdLogoPtr", 4, old->PcdLogoPtr, |
| 308 | new->PcdLogoPtr); |
| 309 | soc_display_upd_value("PcdLogoSize", 4, old->PcdLogoSize, |
| 310 | new->PcdLogoSize); |
| 311 | soc_display_upd_value("PcdRtcLock", 1, old->PcdRtcLock, |
| 312 | new->PcdRtcLock); |
| 313 | soc_display_upd_value("PMIC_I2CBus", 1, |
| 314 | old->PMIC_I2CBus, new->PMIC_I2CBus); |
| 315 | soc_display_upd_value("ISPEnable", 1, |
| 316 | old->ISPEnable, new->ISPEnable); |
| 317 | soc_display_upd_value("ISPPciDevConfig", 1, |
| 318 | old->ISPPciDevConfig, new->ISPPciDevConfig); |
| 319 | } |
| 320 | |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 321 | /* Called at BS_DEV_INIT_CHIPS time -- very early. Just after BS_PRE_DEVICE. */ |
| 322 | static void soc_init(void *chip_info) |
| 323 | { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 324 | printk(BIOS_SPEW, "%s/%s\n", __FILE__, __func__); |
| 325 | soc_init_pre_device(chip_info); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 326 | } |
| 327 | |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 328 | struct chip_operations soc_intel_braswell_ops = { |
| 329 | CHIP_NAME("Intel Braswell SoC") |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 330 | .enable_dev = enable_dev, |
| 331 | .init = soc_init, |
| 332 | }; |
| 333 | |
| 334 | static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) |
| 335 | { |
Lee Leahy | 3247172 | 2015-04-20 15:20:28 -0700 | [diff] [blame] | 336 | printk(BIOS_SPEW, "%s/%s ( %s, 0x%04x, 0x%04x )\n", |
| 337 | __FILE__, __func__, dev_name(dev), vendor, device); |
Lee Leahy | 77ff0b1 | 2015-05-05 15:07:29 -0700 | [diff] [blame] | 338 | if (!vendor || !device) { |
| 339 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 340 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 341 | } else { |
| 342 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 343 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 344 | } |
| 345 | } |
| 346 | |
| 347 | struct pci_operations soc_pci_ops = { |
| 348 | .set_subsystem = &pci_set_subsystem, |
| 349 | }; |