commit 91da91f5d1ac3a1c2671771f18495fc3b703fae5
author Duncan Laurie <dlaurie@chromium.org> Fri Sep 04 13:47:34 2015 -0700
committer Patrick Georgi <pgeorgi@google.com> Thu Sep 10 09:52:25 2015 +0000
tree 795e4c2d974cc85c1cf23b36f9d0e2547d6e53fc
parent 74b964ec4ace463d0b221a369a754bc86776e594

intel/common: Print board ID if enabled

Read and print the board ID if it is enabled in the mainboard.

BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-glados coreboot

Change-Id: I9d50089242b3a2f461dff2b1039adc8f0347179e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f245854b30c40eda38453c1b0ae5d3b8b18c010f
Original-Change-Id: Ifbd7c2666820ea146dc44fbc42bfe201cb227ff6
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297756
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11577
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/common/romstage.c

diff --git a/src/soc/intel/common/romstage.c b/src/soc/intel/common/romstage.c
index 7a05e17..ee9c975 100644
--- a/src/soc/intel/common/romstage.c
+++ b/src/soc/intel/common/romstage.c
@@ -25,6 +25,7 @@
 #include <arch/cbfs.h>
 #include <arch/stages.h>
 #include <arch/early_variables.h>
+#include <boardid.h>
 #include <console/console.h>
 #include <cbmem.h>
 #include <cpu/x86/mtrr.h>
@@ -101,6 +102,13 @@
 	/* Perform SOC specific initialization. */
 	soc_romstage_init(&params);
 
+	/*
+	 * Read and print board version.  Done after SOC romstage
+	 * in case PCH needs to be configured to talk to the EC.
+	 */
+	if (IS_ENABLED(CONFIG_BOARD_ID_AUTO))
+		printk(BIOS_INFO, "MLB: board version %d\n", board_id());
+
 	/* Call into mainboard. */
 	mainboard_romstage_entry(&params);
 	soc_after_ram_init(&params);