Kerry She | 7b7b2c9 | 2011-09-08 21:16:19 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
Paul Menzel | a46a712 | 2013-02-23 18:37:27 +0100 | [diff] [blame] | 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Kerry She | 7b7b2c9 | 2011-09-08 21:16:19 +0800 | [diff] [blame] | 18 | */ |
| 19 | |
| 20 | |
Jens Rottmann | 940095f | 2013-02-20 21:24:20 +0100 | [diff] [blame] | 21 | #ifndef _PLATFORM_CFG_H_ |
| 22 | #define _PLATFORM_CFG_H_ |
Kerry She | 7b7b2c9 | 2011-09-08 21:16:19 +0800 | [diff] [blame] | 23 | |
| 24 | /** |
Edward O'Callaghan | 5760e19 | 2014-01-26 11:45:30 +1100 | [diff] [blame] | 25 | * @def BIOS_SIZE -> BIOS_SIZE_{1,2,4,8,16}M |
| 26 | * |
| 27 | * In SB800, default ROM size is 1M Bytes, if your platform ROM |
Kerry She | 7b7b2c9 | 2011-09-08 21:16:19 +0800 | [diff] [blame] | 28 | * bigger than 1M you have to set the ROM size outside CIMx module and |
| 29 | * before AGESA module get call. |
| 30 | */ |
| 31 | #ifndef BIOS_SIZE |
Edward O'Callaghan | 5760e19 | 2014-01-26 11:45:30 +1100 | [diff] [blame] | 32 | #define BIOS_SIZE ((CONFIG_COREBOOT_ROMSIZE_KB >> 10) - 1) |
| 33 | #endif /* BIOS_SIZE */ |
Kerry She | 7b7b2c9 | 2011-09-08 21:16:19 +0800 | [diff] [blame] | 34 | |
| 35 | /** |
| 36 | * @def SPREAD_SPECTRUM |
| 37 | * @brief |
| 38 | * 0 - Disable Spread Spectrum function |
| 39 | * 1 - Enable Spread Spectrum function |
| 40 | */ |
| 41 | #define SPREAD_SPECTRUM 0 |
| 42 | |
| 43 | /** |
| 44 | * @def SB_HPET_TIMER |
Paul Menzel | 522b556 | 2013-02-21 17:09:01 +0100 | [diff] [blame] | 45 | * @brief |
Kerry She | 7b7b2c9 | 2011-09-08 21:16:19 +0800 | [diff] [blame] | 46 | * 0 - Disable hpet |
| 47 | * 1 - Enable hpet |
| 48 | */ |
| 49 | #define HPET_TIMER 1 |
| 50 | |
| 51 | /** |
| 52 | * @def USB_CONFIG |
| 53 | * @brief bit[0-6] used to control USB |
| 54 | * 0 - Disable |
| 55 | * 1 - Enable |
Kyösti Mälkki | 6533b83 | 2014-06-26 05:30:54 +0300 | [diff] [blame^] | 56 | * Usb Ohci1 Controller (Bus 0 Dev 18 Func0) is define at BIT0 |
| 57 | * Usb Ehci1 Controller (Bus 0 Dev 18 Func2) is define at BIT1 |
| 58 | * Usb Ohci2 Controller (Bus 0 Dev 19 Func0) is define at BIT2 |
| 59 | * Usb Ehci2 Controller (Bus 0 Dev 19 Func2) is define at BIT3 |
| 60 | * Usb Ohci3 Controller (Bus 0 Dev 22 Func0) is define at BIT4 |
| 61 | * Usb Ehci3 Controller (Bus 0 Dev 22 Func2) is define at BIT5 |
| 62 | * Usb Ohci4 Controller (Bus 0 Dev 20 Func5) is define at BIT6 |
Kerry She | 7b7b2c9 | 2011-09-08 21:16:19 +0800 | [diff] [blame] | 63 | */ |
| 64 | #define USB_CONFIG 0x7F |
| 65 | |
| 66 | /** |
| 67 | * @def PCI_CLOCK_CTRL |
Paul Menzel | 522b556 | 2013-02-21 17:09:01 +0100 | [diff] [blame] | 68 | * @brief bit[0-4] used for PCI Slots Clock Control, |
Kerry She | 7b7b2c9 | 2011-09-08 21:16:19 +0800 | [diff] [blame] | 69 | * 0 - disable |
| 70 | * 1 - enable |
| 71 | * PCI SLOT 0 define at BIT0 |
| 72 | * PCI SLOT 1 define at BIT1 |
| 73 | * PCI SLOT 2 define at BIT2 |
| 74 | * PCI SLOT 3 define at BIT3 |
| 75 | * PCI SLOT 4 define at BIT4 |
| 76 | */ |
| 77 | #define PCI_CLOCK_CTRL 0x1F |
| 78 | |
| 79 | /** |
| 80 | * @def SATA_CONTROLLER |
Paul Menzel | 522b556 | 2013-02-21 17:09:01 +0100 | [diff] [blame] | 81 | * @brief INCHIP Sata Controller |
Kerry She | 7b7b2c9 | 2011-09-08 21:16:19 +0800 | [diff] [blame] | 82 | */ |
| 83 | #define SATA_CONTROLLER CIMX_OPTION_ENABLED |
| 84 | |
| 85 | /** |
| 86 | * @def SATA_MODE |
Paul Menzel | 522b556 | 2013-02-21 17:09:01 +0100 | [diff] [blame] | 87 | * @brief INCHIP Sata Controller Mode |
Kerry She | 7b7b2c9 | 2011-09-08 21:16:19 +0800 | [diff] [blame] | 88 | * NOTE: DO NOT ALLOW SATA & IDE use same mode |
| 89 | */ |
Kerry Sheh | 56ed40a | 2011-10-11 17:27:26 +0800 | [diff] [blame] | 90 | #define SATA_MODE CONFIG_SB800_SATA_MODE |
Kerry She | 7b7b2c9 | 2011-09-08 21:16:19 +0800 | [diff] [blame] | 91 | |
| 92 | /** |
Paul Menzel | 522b556 | 2013-02-21 17:09:01 +0100 | [diff] [blame] | 93 | * @brief INCHIP Sata IDE Controller Mode |
Kerry She | 7b7b2c9 | 2011-09-08 21:16:19 +0800 | [diff] [blame] | 94 | */ |
| 95 | #define IDE_LEGACY_MODE 0 |
| 96 | #define IDE_NATIVE_MODE 1 |
| 97 | |
| 98 | /** |
| 99 | * @def SATA_IDE_MODE |
Paul Menzel | 522b556 | 2013-02-21 17:09:01 +0100 | [diff] [blame] | 100 | * @brief INCHIP Sata IDE Controller Mode |
Kerry She | 7b7b2c9 | 2011-09-08 21:16:19 +0800 | [diff] [blame] | 101 | * NOTE: DO NOT ALLOW SATA & IDE use same mode |
| 102 | */ |
| 103 | #define SATA_IDE_MODE IDE_LEGACY_MODE |
| 104 | |
| 105 | /** |
| 106 | * @def EXTERNAL_CLOCK |
| 107 | * @brief 00/10: Reference clock from crystal oscillator via |
| 108 | * PAD_XTALI and PAD_XTALO |
| 109 | * |
| 110 | * @def INTERNAL_CLOCK |
| 111 | * @brief 01/11: Reference clock from internal clock through |
| 112 | * CP_PLL_REFCLK_P and CP_PLL_REFCLK_N via RDL |
| 113 | */ |
| 114 | #define EXTERNAL_CLOCK 0x00 |
| 115 | #define INTERNAL_CLOCK 0x01 |
| 116 | |
| 117 | /* NOTE: inagua have to using internal clock, |
| 118 | * otherwise can not detect sata drive |
| 119 | */ |
| 120 | #define SATA_CLOCK_SOURCE INTERNAL_CLOCK |
| 121 | |
| 122 | /** |
| 123 | * @def SATA_PORT_MULT_CAP_RESERVED |
| 124 | * @brief 1 ON, 0 0FF |
| 125 | */ |
| 126 | #define SATA_PORT_MULT_CAP_RESERVED 1 |
| 127 | |
| 128 | |
| 129 | /** |
| 130 | * @def AZALIA_AUTO |
| 131 | * @brief Detect Azalia controller automatically. |
| 132 | * |
| 133 | * @def AZALIA_DISABLE |
| 134 | * @brief Disable Azalia controller. |
| 135 | |
| 136 | * @def AZALIA_ENABLE |
| 137 | * @brief Enable Azalia controller. |
| 138 | */ |
| 139 | #define AZALIA_AUTO 0 |
| 140 | #define AZALIA_DISABLE 1 |
| 141 | #define AZALIA_ENABLE 2 |
| 142 | |
| 143 | /** |
Paul Menzel | 522b556 | 2013-02-21 17:09:01 +0100 | [diff] [blame] | 144 | * @brief INCHIP HDA controller |
Kerry She | 7b7b2c9 | 2011-09-08 21:16:19 +0800 | [diff] [blame] | 145 | */ |
| 146 | #define AZALIA_CONTROLLER AZALIA_AUTO |
| 147 | |
| 148 | /** |
| 149 | * @def AZALIA_PIN_CONFIG |
| 150 | * @brief |
| 151 | * 0 - disable |
| 152 | * 1 - enable |
| 153 | */ |
| 154 | #define AZALIA_PIN_CONFIG 1 |
| 155 | |
| 156 | /** |
| 157 | * @def AZALIA_SDIN_PIN |
| 158 | * @brief |
| 159 | * SDIN0 is define at BIT0 & BIT1 |
| 160 | * 00 - GPIO PIN |
| 161 | * 01 - Reserved |
| 162 | * 10 - As a Azalia SDIN pin |
| 163 | * SDIN1 is define at BIT2 & BIT3 |
| 164 | * SDIN2 is define at BIT4 & BIT5 |
| 165 | * SDIN3 is define at BIT6 & BIT7 |
| 166 | */ |
| 167 | //#define AZALIA_SDIN_PIN 0xAA |
| 168 | #define AZALIA_SDIN_PIN 0x2A |
| 169 | |
| 170 | /** |
| 171 | * @def GPP_CONTROLLER |
| 172 | */ |
| 173 | #define GPP_CONTROLLER CIMX_OPTION_ENABLED |
| 174 | |
| 175 | /** |
| 176 | * @def GPP_CFGMODE |
| 177 | * @brief GPP Link Configuration |
| 178 | * four possible configuration: |
| 179 | * GPP_CFGMODE_X4000 |
| 180 | * GPP_CFGMODE_X2200 |
| 181 | * GPP_CFGMODE_X2110 |
| 182 | * GPP_CFGMODE_X1111 |
| 183 | */ |
| 184 | #define GPP_CFGMODE GPP_CFGMODE_X1111 |
| 185 | |
| 186 | /** |
| 187 | * @def NB_SB_GEN2 |
| 188 | * 0 - Disable |
| 189 | * 1 - Enable |
| 190 | */ |
| 191 | #define NB_SB_GEN2 TRUE |
| 192 | |
| 193 | /** |
| 194 | * @def SB_GEN2 |
| 195 | * 0 - Disable |
| 196 | * 1 - Enable |
| 197 | */ |
| 198 | #define SB_GPP_GEN2 TRUE |
| 199 | |
| 200 | /** |
| 201 | * @def SB_GPP_UNHIDE_PORTS |
| 202 | * TRUE - ports visable always, even port empty |
| 203 | * FALSE - ports invisable if port empty |
| 204 | */ |
| 205 | #define SB_GPP_UNHIDE_PORTS FALSE |
| 206 | |
| 207 | /** |
| 208 | * @def GEC_CONFIG |
| 209 | * 0 - Enable |
| 210 | * 1 - Disable |
| 211 | */ |
| 212 | #define GEC_CONFIG 0 |
| 213 | |
| 214 | /** |
| 215 | * @def SIO_HWM_BASE_ADDRESS Super IO HWM base address |
| 216 | */ |
| 217 | #define SIO_HWM_BASE_ADDRESS 0x290 |
| 218 | |
| 219 | #endif |