blob: 360b2abf693ffcdc22cd6e2b839b502b3072b857 [file] [log] [blame]
Uwe Hermannc70e9fc2010-02-15 23:10:19 +00001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2007-2009 coresystems GmbH
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
15## You should have received a copy of the GNU General Public License
16## along with this program; if not, write to the Free Software
Paul Menzela46a7122013-02-23 18:37:27 +010017## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Uwe Hermannc70e9fc2010-02-15 23:10:19 +000018##
Patrick Georgi0588d192009-08-12 15:00:51 +000019
Kyösti Mälkkieb5e28f2012-02-24 16:08:18 +020020config NORTHBRIDGE_INTEL_I945
Patrick Georgi0588d192009-08-12 15:00:51 +000021 bool
Kyösti Mälkkieb5e28f2012-02-24 16:08:18 +020022
23if NORTHBRIDGE_INTEL_I945
24
25config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
26 def_bool y
Kyösti Mälkki032c23d2013-07-01 11:21:53 +030027 select MMCONF_SUPPORT
28 select MMCONF_SUPPORT_DEFAULT
Kyösti Mälkki6455b012014-06-13 11:07:34 +030029 select DYNAMIC_CBMEM
Jens Rottmann0d11f2d2010-08-26 12:46:02 +000030 select HAVE_DEBUG_RAM_SETUP
Denis 'GNUtoo' Cariklifd39ddd2013-06-04 04:48:11 +020031 select LAPIC_MONOTONIC_TIMER
Uwe Hermann81b3c0a2009-10-30 12:56:59 +000032
Kyösti Mälkkieb5e28f2012-02-24 16:08:18 +020033config NORTHBRIDGE_INTEL_SUBTYPE_I945GC
34 def_bool n
35config NORTHBRIDGE_INTEL_SUBTYPE_I945GM
36 def_bool n
Peter Stugee4bc0f62010-10-01 09:13:18 +000037
Kyösti Mälkki032c23d2013-07-01 11:21:53 +030038config BOOTBLOCK_NORTHBRIDGE_INIT
39 string
40 default "northbridge/intel/i945/bootblock.c"
41
Stefan Reinauerbccbbe62010-12-19 21:20:14 +000042config VGA_BIOS_ID
Uwe Hermann81b3c0a2009-10-30 12:56:59 +000043 string
44 default "8086,27a2"
Patrick Georgi77d66832010-10-01 08:02:45 +000045
46config CHANNEL_XOR_RANDOMIZATION
47 bool
48 default n
Patrick Georgi77d66832010-10-01 08:02:45 +000049
50config OVERRIDE_CLOCK_DISABLE
51 bool
52 default n
Patrick Georgi77d66832010-10-01 08:02:45 +000053 help
54 Usually system firmware turns off system memory clock
55 signals to unused SO-DIMM slots to reduce EMI and power
56 consumption.
57 However, some boards do not like unused clock signals to
58 be disabled.
59
60config MAXIMUM_SUPPORTED_FREQUENCY
61 int
62 default 0
Patrick Georgi77d66832010-10-01 08:02:45 +000063 help
64 If non-zero, this designates the maximum DDR frequency
65 the board supports, despite what the chipset should be
66 capable of.
Peter Stugee4bc0f62010-10-01 09:13:18 +000067
Peter Stuge751508a2012-01-27 22:17:09 +010068config CHECK_SLFRCS_ON_RESUME
69 def_bool n
70 help
71 On some boards it may be neccessary to hard reset early
72 during resume from S3 if the SLFRCS register indicates that
73 a memory channel is not guaranteed to be in self-refresh.
74 On other boards the check always creates a false positive,
75 effectively making it impossible to resume.
76
Peter Stugee4bc0f62010-10-01 09:13:18 +000077endif