Marc Jones | 392bcca | 2020-09-28 11:19:39 -0600 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <acpi/acpi_gnvs.h> |
| 4 | #include <acpi/acpigen.h> |
| 5 | #include <arch/smp/mpspec.h> |
| 6 | #include <assert.h> |
| 7 | #include <cbmem.h> |
| 8 | #include <cpu/intel/turbo.h> |
| 9 | #include <device/mmio.h> |
| 10 | #include <device/pci.h> |
| 11 | #include <intelblocks/acpi.h> |
| 12 | #include <soc/acpi.h> |
| 13 | #include <soc/cpu.h> |
| 14 | #include <soc/iomap.h> |
| 15 | #include <soc/msr.h> |
| 16 | #include <soc/pci_devs.h> |
| 17 | #include <soc/pm.h> |
| 18 | #include <soc/soc_util.h> |
Arthur Heymans | 6408ada | 2020-11-12 17:33:00 +0100 | [diff] [blame^] | 19 | #include <soc/util.h> |
Marc Jones | 392bcca | 2020-09-28 11:19:39 -0600 | [diff] [blame] | 20 | |
Marc Jones | 392bcca | 2020-09-28 11:19:39 -0600 | [diff] [blame] | 21 | /* TODO: Check if the common/acpi weak function can be used */ |
| 22 | unsigned long acpi_fill_mcfg(unsigned long current) |
| 23 | { |
| 24 | current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, |
| 25 | CONFIG_MMCONF_BASE_ADDRESS, 0, 0, 255); |
| 26 | return current; |
| 27 | } |
| 28 | |
| 29 | void acpi_create_gnvs(struct global_nvs *gnvs) |
| 30 | { |
| 31 | /* CPU core count */ |
| 32 | gnvs->pcnt = dev_count_cpu(); |
| 33 | printk(BIOS_DEBUG, "%s gnvs->pcnt: %d\n", __func__, gnvs->pcnt); |
| 34 | } |
| 35 | |
| 36 | int soc_madt_sci_irq_polarity(int sci) |
| 37 | { |
| 38 | if (sci >= 20) |
| 39 | return MP_IRQ_POLARITY_LOW; |
| 40 | else |
| 41 | return MP_IRQ_POLARITY_HIGH; |
| 42 | } |
| 43 | |
Marc Jones | 70ddbd8 | 2020-09-28 12:25:03 -0600 | [diff] [blame] | 44 | uint32_t soc_read_sci_irq_select(void) |
| 45 | { |
| 46 | struct device *dev = PCH_DEV_PMC; |
| 47 | |
| 48 | if (!dev) |
| 49 | return 0; |
| 50 | |
| 51 | return pci_read_config32(dev, PMC_ACPI_CNT); |
| 52 | } |
| 53 | |
Marc Jones | 2560ad3 | 2020-09-28 15:23:35 -0600 | [diff] [blame] | 54 | void soc_fill_fadt(acpi_fadt_t *fadt) |
| 55 | { |
| 56 | /* Clear flags set by common/block/acpi/acpi.c acpi_fill_fadt() */ |
Morgan Jang | 160cb33 | 2020-10-27 11:34:43 +0800 | [diff] [blame] | 57 | fadt->flags &= ~(ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE); |
Marc Jones | 2560ad3 | 2020-09-28 15:23:35 -0600 | [diff] [blame] | 58 | } |
| 59 | |
Marc Jones | 521a03f | 2020-10-19 13:46:59 -0600 | [diff] [blame] | 60 | void uncore_inject_dsdt(const struct device *device) |
Marc Jones | 392bcca | 2020-09-28 11:19:39 -0600 | [diff] [blame] | 61 | { |
| 62 | struct iiostack_resource stack_info = {0}; |
| 63 | |
Marc Jones | 2c70716 | 2020-10-31 15:29:14 -0600 | [diff] [blame] | 64 | /* Only add RTxx entries once. */ |
| 65 | if (device->bus->secondary != 0) |
| 66 | return; |
| 67 | |
Marc Jones | 392bcca | 2020-09-28 11:19:39 -0600 | [diff] [blame] | 68 | get_iiostack_info(&stack_info); |
| 69 | |
| 70 | acpigen_write_scope("\\_SB"); |
| 71 | |
| 72 | for (uint8_t stack = 0; stack < stack_info.no_of_stacks; ++stack) { |
| 73 | const STACK_RES *ri = &stack_info.res[stack]; |
| 74 | char rtname[16]; |
| 75 | |
| 76 | snprintf(rtname, sizeof(rtname), "RT%02x", stack); |
| 77 | |
| 78 | acpigen_write_name(rtname); |
| 79 | printk(BIOS_DEBUG, "\tCreating ResourceTemplate %s for stack: %d\n", |
| 80 | rtname, stack); |
| 81 | |
| 82 | acpigen_write_resourcetemplate_header(); |
| 83 | |
| 84 | /* bus resource */ |
| 85 | acpigen_resource_word(2, 0xc, 0, 0, ri->BusBase, ri->BusLimit, |
| 86 | 0x0, (ri->BusLimit - ri->BusBase + 1)); |
| 87 | |
| 88 | /* additional io resources on socket 0 bus 0 */ |
| 89 | if (stack == 0) { |
| 90 | /* ACPI 6.4.2.5 I/O Port Descriptor */ |
| 91 | acpigen_write_io16(0xCF8, 0xCFF, 0x1, 0x8, 1); |
| 92 | |
| 93 | /* IO decode CF8-CFF */ |
| 94 | acpigen_resource_word(1, 0xc, 0x3, 0, 0x0000, 0x03AF, 0, 0x03B0); |
| 95 | acpigen_resource_word(1, 0xc, 0x3, 0, 0x03E0, 0x0CF7, 0, 0x0918); |
| 96 | acpigen_resource_word(1, 0xc, 0x3, 0, 0x03B0, 0x03BB, 0, 0x000C); |
| 97 | acpigen_resource_word(1, 0xc, 0x3, 0, 0x03C0, 0x03DF, 0, 0x0020); |
| 98 | } |
| 99 | |
| 100 | /* IO resource */ |
| 101 | acpigen_resource_word(1, 0xc, 0x3, 0, ri->PciResourceIoBase, |
| 102 | ri->PciResourceIoLimit, 0x0, |
| 103 | (ri->PciResourceIoLimit - ri->PciResourceIoBase + 1)); |
| 104 | |
| 105 | /* additional mem32 resources on socket 0 bus 0 */ |
| 106 | if (stack == 0) { |
| 107 | acpigen_resource_dword(0, 0xc, 3, 0, VGA_BASE_ADDRESS, |
| 108 | (VGA_BASE_ADDRESS + VGA_BASE_SIZE - 1), 0x0, |
| 109 | VGA_BASE_SIZE); |
| 110 | acpigen_resource_dword(0, 0xc, 1, 0, SPI_BASE_ADDRESS, |
| 111 | (SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0, |
| 112 | SPI_BASE_SIZE); |
| 113 | } |
| 114 | |
| 115 | /* Mem32 resource */ |
| 116 | acpigen_resource_dword(0, 0xc, 1, 0, ri->PciResourceMem32Base, |
| 117 | ri->PciResourceMem32Limit, 0x0, |
| 118 | (ri->PciResourceMem32Limit - ri->PciResourceMem32Base + 1)); |
| 119 | |
| 120 | /* Mem64 resource */ |
| 121 | acpigen_resource_qword(0, 0xc, 1, 0, ri->PciResourceMem64Base, |
| 122 | ri->PciResourceMem64Limit, 0x0, |
| 123 | (ri->PciResourceMem64Limit - ri->PciResourceMem64Base + 1)); |
| 124 | |
| 125 | acpigen_write_resourcetemplate_footer(); |
| 126 | } |
| 127 | acpigen_pop_len(); |
| 128 | } |
| 129 | |
Marc Jones | 7a25fb8 | 2020-10-19 16:32:05 -0600 | [diff] [blame] | 130 | /* TODO: See if we can use the common generate_p_state_entries */ |
| 131 | void soc_power_states_generation(int core, int cores_per_package) |
Marc Jones | 392bcca | 2020-09-28 11:19:39 -0600 | [diff] [blame] | 132 | { |
| 133 | int ratio_min, ratio_max, ratio_turbo, ratio_step; |
| 134 | int coord_type, power_max, power_unit, num_entries; |
| 135 | int ratio, power, clock, clock_max; |
| 136 | msr_t msr; |
| 137 | |
| 138 | /* Determine P-state coordination type from MISC_PWR_MGMT[0] */ |
| 139 | msr = rdmsr(MSR_MISC_PWR_MGMT); |
| 140 | if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS) |
| 141 | coord_type = SW_ANY; |
| 142 | else |
| 143 | coord_type = HW_ALL; |
| 144 | |
| 145 | /* Get bus ratio limits and calculate clock speeds */ |
| 146 | msr = rdmsr(MSR_PLATFORM_INFO); |
| 147 | ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */ |
| 148 | |
| 149 | /* Determine if this CPU has configurable TDP */ |
| 150 | if (cpu_config_tdp_levels()) { |
| 151 | /* Set max ratio to nominal TDP ratio */ |
| 152 | msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); |
| 153 | ratio_max = msr.lo & 0xff; |
| 154 | } else { |
| 155 | /* Max Non-Turbo Ratio */ |
| 156 | ratio_max = (msr.lo >> 8) & 0xff; |
| 157 | } |
| 158 | clock_max = ratio_max * CONFIG_CPU_BCLK_MHZ; |
| 159 | |
| 160 | /* Calculate CPU TDP in mW */ |
| 161 | msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); |
| 162 | power_unit = 2 << ((msr.lo & 0xf) - 1); |
| 163 | msr = rdmsr(MSR_PKG_POWER_SKU); |
| 164 | power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; |
| 165 | |
| 166 | /* Write _PCT indicating use of FFixedHW */ |
| 167 | acpigen_write_empty_PCT(); |
| 168 | |
| 169 | /* Write _PPC with no limit on supported P-state */ |
| 170 | acpigen_write_PPC_NVS(); |
| 171 | |
| 172 | /* Write PSD indicating configured coordination type */ |
| 173 | acpigen_write_PSD_package(core, 1, coord_type); |
| 174 | |
| 175 | /* Add P-state entries in _PSS table */ |
| 176 | acpigen_write_name("_PSS"); |
| 177 | |
| 178 | /* Determine ratio points */ |
| 179 | ratio_step = PSS_RATIO_STEP; |
| 180 | num_entries = ((ratio_max - ratio_min) / ratio_step) + 1; |
| 181 | if (num_entries > PSS_MAX_ENTRIES) { |
| 182 | ratio_step += 1; |
| 183 | num_entries = ((ratio_max - ratio_min) / ratio_step) + 1; |
| 184 | } |
| 185 | |
| 186 | /* P[T] is Turbo state if enabled */ |
| 187 | if (get_turbo_state() == TURBO_ENABLED) { |
| 188 | /* _PSS package count including Turbo */ |
| 189 | acpigen_write_package(num_entries + 2); |
| 190 | |
| 191 | msr = rdmsr(MSR_TURBO_RATIO_LIMIT); |
| 192 | ratio_turbo = msr.lo & 0xff; |
| 193 | |
| 194 | /* Add entry for Turbo ratio */ |
| 195 | acpigen_write_PSS_package( |
| 196 | clock_max + 1, /* MHz */ |
| 197 | power_max, /* mW */ |
| 198 | PSS_LATENCY_TRANSITION, /* lat1 */ |
| 199 | PSS_LATENCY_BUSMASTER, /* lat2 */ |
| 200 | ratio_turbo << 8, /* control */ |
| 201 | ratio_turbo << 8); /* status */ |
| 202 | } else { |
| 203 | /* _PSS package count without Turbo */ |
| 204 | acpigen_write_package(num_entries + 1); |
| 205 | } |
| 206 | |
| 207 | /* First regular entry is max non-turbo ratio */ |
| 208 | acpigen_write_PSS_package( |
| 209 | clock_max, /* MHz */ |
| 210 | power_max, /* mW */ |
| 211 | PSS_LATENCY_TRANSITION, /* lat1 */ |
| 212 | PSS_LATENCY_BUSMASTER, /* lat2 */ |
| 213 | ratio_max << 8, /* control */ |
| 214 | ratio_max << 8); /* status */ |
| 215 | |
| 216 | /* Generate the remaining entries */ |
| 217 | for (ratio = ratio_min + ((num_entries - 1) * ratio_step); |
| 218 | ratio >= ratio_min; ratio -= ratio_step) { |
| 219 | |
| 220 | /* Calculate power at this ratio */ |
| 221 | power = calculate_power(power_max, ratio_max, ratio); |
| 222 | clock = ratio * CONFIG_CPU_BCLK_MHZ; |
| 223 | //clock = 1; |
| 224 | acpigen_write_PSS_package( |
| 225 | clock, /* MHz */ |
| 226 | power, /* mW */ |
| 227 | PSS_LATENCY_TRANSITION, /* lat1 */ |
| 228 | PSS_LATENCY_BUSMASTER, /* lat2 */ |
| 229 | ratio << 8, /* control */ |
| 230 | ratio << 8); /* status */ |
| 231 | } |
| 232 | |
| 233 | /* Fix package length */ |
| 234 | acpigen_pop_len(); |
| 235 | } |
| 236 | |
| 237 | unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current) |
| 238 | { |
| 239 | struct device *cpu; |
| 240 | uint8_t num_cpus = 0; |
| 241 | |
| 242 | for (cpu = all_devices; cpu; cpu = cpu->next) { |
| 243 | if ((cpu->path.type != DEVICE_PATH_APIC) || |
| 244 | (cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { |
| 245 | continue; |
| 246 | } |
| 247 | if (!cpu->enabled) |
| 248 | continue; |
| 249 | current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, |
| 250 | num_cpus, cpu->path.apic.apic_id); |
| 251 | num_cpus++; |
| 252 | } |
| 253 | |
| 254 | return current; |
| 255 | } |